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| 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR Y Performs Complete CSMA CD Medium Access Control (MAC) Functions Independently of CPU IEEE 802 3 (EOC) Frame Delimiting Supports Industry Standard LANs IEEE TYPE 10BASE-T IEEE TYPE 10BASE5 (Ethernet ) IEEE TYPE 10BASE2 (Cheapernet) IEEE TYPE 1BASE5 (StarLAN) and the Proposed Standard 10BASE-F Proprietary CSMA CD Networks Up to 20 Mb s On-Chip Memory Management Automatic Buffer Chaining Buffer Reclamation after Receipt of Bad Frames Optional Save Bad Frames 32-Bit Segmented or Linear (Flat) Memory Addressing Formats Network Management and Diagnostics Monitor Mode 32-Bit Statistical Counters 82586 Software Compatible Self-Test Diagnostics Y Y Optimized CPU Interface Optimized Bus Interface to Intel's i486 TM DX i486 TM SX i487 TM SX and 80960CA Processors 33 MHz 25 MHz 20 MHz and 16 MHz Clock Frequencies Supports Big Endian and Little Endian Byte Ordering 32-Bit Bus Master Interface 106 MB s Bus Bandwidth Burst Bus Transfers Bus Throttle Timers Transfers Data at 100% of Serial Bandwidth 128-Byte Receive FIFO 64-Byte Transmit FIFO Configurable Initialization Root for Data Structures High-Speed 5V CHMOS Technology IV Y Y Y Y Y Y 132-Pin Plastic Quad Flat Pack (PQFP) and PGA Package (See Packaging Spec Order No 240800-001 Package Type KU and A) Y Y i486 is a trademark of Intel Corporation Ethernet is a registered trademark of Xerox Corporation CHMOS is a patented process of Intel Corporation 290218 - 1 Figure 1 82596CA Block Diagram Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1996 October 1995 Order Number 290218-006 82596CA 82596CA High-Performance 32-Bit Local Area Network Coprocessor CONTENTS INTRODUCTION PIN DESCRIPTIONS 82596 AND HOST CPU INTERACTION 82596 BUS INTERFACE 82596 MEMORY ADDRESSING 82596 SYSTEM MEMORY STRUCTURE TRANSMIT AND RECEIVE MEMORY STRUCTURES TRANSMITTING FRAMES RECEIVING FRAMES 82596 NETWORK MANAGEMENT AND DIAGNOSTICS NETWORK PLANNING AND MAINTENANCE STATION DIAGNOSTICS AND SELFTEST 82586 SOFTWARE COMPATIBILITY INITIALIZING THE 82596 SYSTEM CONFIGURATION POINTER (SCP) Writing the Sysbus INTERMEDIATE SYSTEM CONFIGURATION POINTER (ISCP) INITIALIZATION PROCESS CONTROLLING THE 82596CA 82596 CPU ACCESS INTERFACE (PORT) MEMORY ADDRESSING FORMATS LITTLE ENDIAN AND BIG ENDIAN BYTE ORDERING COMMAND UNIT (CU) RECEIVE UNIT (RU) 2 PAGE 3 7 11 11 11 13 14 17 18 18 20 21 21 21 21 22 CONTENTS SYSTEM CONTROL BLOCK (SCB) SCB OFFSET ADDRESSES CBL Offset (Address) RFA Offset (Address) SCB STATISTICAL COUNTERS Statistical Counter Operation ACTION COMMANDS AND OPERATING MODES NOP Individual Address Setup Configure Multicast-Setup Transmit Jamming Rules TDR Dump Diagnose RECEIVE FRAME DESCRIPTOR Simplified Memory Structure Flexible Memory Structure Receive Buffer Descriptor (RBD) PGA PACKAGE THERMAL SPECIFICATIONS ELECTRICAL AND TIMING CHARACTERISTICS Absolute Maximum Ratings DC Characteristics AC Characteristics 82596CA C-Step Input Output System Timings Transmit Receive Clock Parameters 82596CA BUS Operation System Interface AC Timing Characteristics Input Waveforms Serial AC Timing Characteristics OUTLINE DIAGRAMS REVISION HISTORY PAGE 27 30 30 30 31 31 32 33 33 34 40 41 43 44 46 49 50 50 51 52 57 57 57 57 58 58 63 66 67 68 70 72 76 23 23 24 24 24 25 26 26 82596CA tallies channel activity indicators optional capture of all frames regardless of destination address (promiscuous mode) optional capture of errored or collided frames and time domain reflectometry for locating fault points on the network cable The statistical counters in 32-bit segmented and linear modes are 32-bits each and include CRC errors alignment errors overrun errors resource errors short frames and received collisions The 82596CA also features a monitor mode for network analysis In this mode the 82596CA can capture status bytes and update statistical counters of frames monitored on the link without transferring the contents of the frames to memory This can be done concurrently while transmitting and receiving frames destined for that station The 82596CA can be used in both baseband and broadband networks It can be configured for maximum network efficiency (minimum contention overhead) with networks of any length Its highly flexible CSMA CD unit supports address field lengths of zero through six bytes for IEEE 802 3 Ethernet frame delimitation It also supports 16- or 32-bit cyclic redundancy checks The CRC can be transferred directly to memory for receive operations or dynamically inserted for transmit operations The CSMA CD unit can also be configured for full duplex operation for high throughput in point-to-point connections The 82596 C-step incorporates several new features not found in previous steppings The following is a summary of the 82596 C-step's new features INTRODUCTION The 82596CA is an intelligent high-performance 32-bit Local Area Network coprocessor The 82596CA implements the CSMA CD access method and can be configured to support all existing IEEE 802 3 standards TYPEs 10BASE-T 10BASE5 10BASE2 1BASE5 and 10BROAD36 It can also be used to implement the proposed standard TYPE 10BASE-F The 82596CA performs high-level commands command chaining and interprocessor communications via shared memory thus relieving the host CPU of many tasks associated with network control All time-critical functions are performed independently of the CPU this increases network performance and efficiency The 82596CA bus interface is optimized for Intel's i486 TM SX i486 TM DX i487 TM SX 80960CA and 80960KB processors The 82596CA implements all IEEE 802 3 Medium Access Control and channel interface functions these include framing preamble generation and stripping source address generation destination address checking short-frame detection and automatic length-field handling Data rates up to 20 Mb s are supported The 82596CA provides a powerful host system interface It manages memory structures automatically with command chaining and bidirectional data chaining An on-chip DMA controller manages four channels this allows autonomous transfer of data blocks (buffers and frames) and relieves the CPU of byte transfer overhead Buffers containing errored or collided frames can be automatically recovered without CPU intervention The 82596CA provides an upgrade path for existing 82586 software drivers by providing an 82586-software-compatible mode that supports the current 82586 memory structure The 82586CA also has a Flexible memory structure and a Simplified memory structure The 82596CA can address up to 4 gigabytes of memory The 82596CA supports Little Endian and Big Endian byte ordering The 82596CA bus interface can achieve a burst transfer rate of 106 MB s at 33 MHz The bus interface employs bus throttle timers to regulate 82596CA bus use Two large independent FIFOs 128 bytes for Receive and 64 bytes for Transmit tolerate long bus latencies and provide programmable thresholds that allow the user to optimize bus overhead for any worst-case bus latency The highperformance bus is capable of back-to-back transmission and reception during the IEEE 802 3 9 6-ms Interframe Spacing (IFS) period The 82596CA provides a wide range of diagnostics and network management functions these include internal and external loopback exception condition The 82596 C-step fixes Errata found in the A1 and B steppings The 82596 C-step has improved AC timings over both the A and B steppings The 82596 C-step has a New Enhanced Big Endian Mode where in Linear Addressing Mode true 32-bit Big Endian functionality is achieved New Enhanced Big Endian Mode is enabled by setting bit 7 of the SYSBUS byte This mode is software compatible with the big endian mode of the B-step with one exception no 32-bit addresses need to be swapped by software in the C-step In this new mode the 82596 C-step treats 32-bit address pointers as true 32-bit entities and the SCB absolute address and statistical counters are still treated as two 16-bit big endian entities Not setting this mode will configure the 82596 C-step to be 100% compatible to the A1-step big endian mode The 82596 C-step is hardware and software compatible to both the A1 and B steppings allowing for easy ``drop-in'' to current designs Pinout and control structures remain unchanged 3 82596CA The 82596CA is fabricated with Intel's reliable 5-V CHMOS IV (process 648 8) technology It is available in a 132-pin PQFP or PGA package 290218 - 2 Figure 2 82596CA PQFP Pin Configuration 4 82596CA 290218 - 3 Figure 3 82596CA PGA Pinout 5 82596CA 82596CA PGA Cross Reference by Pin Name Address Signal A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pin No N9 M9 M10 P11 N11 P12 M11 N12 M12 P13 L12 N13 M13 P14 K12 N14 J12 K13 M14 H12 K14 G12 F14 F12 F13 D14 E12 D13 D12 C14 Data Signal D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Pin No J2 H3 G2 G3 G1 D1 C1 F3 D2 C2 E3 D3 B2 B1 C3 A1 B3 C4 A2 C5 A3 B4 A4 C6 B5 C7 A5 B8 C8 A9 C9 B9 Control Signal ADS AHOLD BE0 BE1 BE2 BE3 BLAST BOFF BRDY BREQ BS16 CA CLK DP0 DP1 DP2 DP3 HLDA HOLD INT INT LE BE LOCK PCHK PORT READY RESET WR Pin No M5 N5 M7 P5 M8 P9 N2 N6 M1 P4 N1 P3 J3 L2 L3 L1 K3 M6 P2 N3 B14 M4 P1 M2 M3 B13 N4 Serial Interface Signal CDT CRS CTS LPBK RTS RxC RxD TxC TxD Pin No A13 A14 C11 A12 C10 B11 B12 C12 A11 VCC Pin No B6 B7 B10 C13 E2 E13 F2 G13 H2 H13 J13 K2 L13 N7 N8 N10 VSS Pin No A6 A7 A8 A10 E1 E14 F1 G14 H1 H14 J1 J14 K1 L14 P6 P7 P8 P10 6 82596CA PIN DESCRIPTIONS Symbol CLK PQFP Pin No 9 Type I Name and Function CLOCK The system clock input provides the fundamental timing for the 82596 It is a 1X CLK input used to generate the 82596 clock and requires TTL levels All external timing parameters are specified in reference to the rising edge of CLK DATA BUS The 32 Data Bus lines are bidirectional tri-state lines that provide the general purpose data path between the 82596 and memory With the 82596 the bus can be either 16 or 32 bits wide this is determined by the BS16 signal The 82596 always drives all 32 data lines during Write operations even with a 16-bit bus D31 - D0 are floated after a Reset or when the bus is not acquired These lines are inputs during a CPU Port access in this mode the CPU writes the next address to the 82596 through the data lines During PORT commands (Relocatable SCP Self-Test Reset and Dump) the address must be aligned to a 16-byte boundary This frees the D3 -D0 lines so they can be used to distinguish the commands The following is a summary of the decoding data D0 0 0 1 1 DP0-DP3 4-7 IO D1 0 1 0 1 D2 0 0 0 0 D3 0 0 0 0 D31 - D4 0000 ADDR ADDR ADDR Function Reset Relocatable SCP Self-Test Dump Command D0-D31 14-53 IO DATA PARITY These are tri-stated data parity pins There is one parity line for each byte of the data bus The 82596 drives them with even-parity information during write operations having the same timing as data writes Likewise even-parity information with the same timing as read information must be driven back to the 82596 over these pins to ensure that the correct parity check status is indicated by the 82596 PARITY CHECK This pin is driven high one clock after RDY to inform Read operations of the parity status of data sampled at the end of the previous clock cycle When driven low it indicates that incorrect parity data has been sampled It only checks the parity status of enabled bytes which are indicated by the Byte Enable and Bus Size signals PCHK is only valid for one clock time after data read is returned to the 82596 i e it is inactive (high) at all other times ADDRESS LINES These 30 tri-stated Address lines output the address bits required for memory operation These lines are floated after a Reset or when the bus is not acquired BYTE ENABLE These tri-stated signals are used to indicate which bytes are involved with the current memory access The number of Byte Enable signals asserted indicates the physical size of the data being transferred (1 2 3 or 4 bytes) BE0 indicates D7 - D0 BE1 indicates D15 - D8 BE2 indicates D23 - D16 BE3 indicates D31 - D24 These lines are floated after a Reset or when the bus is not acquired WRITE READ This dual function pin is used to distinguish Write and Read cycles This line is floated after a Reset or when the bus is not acquired 7 PCHK 127 O A31-A2 70-108 O BE3 -BE0 109-114 O WR 120 O 82596CA PIN DESCRIPTIONS (Continued) Symbol ADS PQFP Pin No 124 Type O Name and Function ADDRESS STATUS The 82596 uses this tri-state pin to indicate to indicate that a valid bus cycle has begun and that A31 - A2 BE3 - BE0 and W R are being driven It is asserted during t1 bus states This line is floated after a Reset or when the bus is not acquired READY Active low This signal is the acknowledgment from addressed memory that the transfer cycle can be completed When high it causes wait states to be inserted It is ignored at the end of the first clock of the bus cycle's data cycle This active-low signal does not have an internal pull-up resistor This signal must meet the setup and hold times to operate correctly BURST READY Active low Burst Ready like RDY indicates that the external system has presented valid data on the data pins in response to a Read or that the external system has accepted the 82596 data in response to a Write request Also like RDY this signal is ignored at the end of the first clock in a bus cycle If the 82596 can still receive data from the previous cycle ADS will not be asserted in the next clock cycle however Address and Byte Enable will change to reflect the next data item expected by the 82596 BRDY will be sampled during each succeeding clock and if active the data on the pins will be strobed to the 82596 or to external memory (read write) BRDY operates exactly like READY during the last data cycle of a burst sequence and during nonburstable cycles BURST LAST A signal (active low) on this tri-state pin indicates that the burst cycle is finished and when BRDY is next returned it will be treated as a normal ready i e another set of addresses will be driven with ADS or the bus will go idle BLAST is not asserted if the bus is not acquired ADDRESS HOLD This hold signal is active high it allows another bus master to access the 82596 address bus In a system where an 82596 and an i486 processor share the local bus AHOLD allows the cache controller to make a cache invalidation cycle while the 82596 holds the address lines In response to a signal on this pin the 82596 immediately (i e during the next clock) stops driving the entire address bus (A31- A2) the rest of the bus can remain active For example data can be returned for a previously specified bus cycle during Address Hold The 82596 will not begin another bus cycle while AHOLD is active BACKOFF This signal is active low it informs the 82596 that another bus master requires access to the bus before the 82596 bus cycle completes The 82596 immediately (i e during the next clock) floats its bus Any data returned to the 82596 while BOFF is asserted is ignored BOFF has higher priority than RDY or BRDY if two such signals are returned in the same clock period BOFF is given preference The 82596 remains in Hold until BOFF goes high then the 82596 resumes its bus cycle by driving out the address and status and asserting ADS LOCK This tri-state pin is used to distinguish locked and unlocked bus cycles LOCK generates a semaphore handshake to the CPU LOCK can be active for several memory cycles it goes active during the first locked memory cycle (t1) and goes inactive at the last locked cycle (t2) This line is floated after a Reset or when the bus is not acquired LOCK can be disabled via the sysbus byte in software RDY 130 I BRDY 2 I BLAST 128 O AHOLD 117 I BOFF 116 I LOCK 126 O 8 82596CA PIN DESCRIPTIONS (Continued) Symbol BS16 PQFP Pin No 129 Type I Name and Function BUS SIZE This signal allows the 82596CA to work with either 16- or 32-bit bytes Inserting BS16 low causes the 82596 to perform two 16bit memory accesses when transferring 32-bit data In little endian mode the D15 - D0 lines are driven when BS16 is inserted in Big Endian mode the D31 - D16 lines are driven HOLD The HOLD signal is active high the 82596 uses it to request local bus mastership In normal operation HOLD goes inactive before HLDA The 82596 can be forced off the bus by deasserting HLDA or if the bus throttle timers expire HOLD ACKNOWLEDGE The HLDA signal is active high it indicates that bus mastership has been given to the 82596 HLDA is internally synchronized after HOLD is detected low the CPU drives HLDA low NOTE Do not connect HLDA to VCC it will cause a deadlock A user wanting to give the 82596 permanent access to the bus should connect HLDA to HOLD If HLDA goes inactive before HOLD the 82596 will release the bus (by deasserting HOLD) within a maximum of within a specified number of bus cycles as specified in the 82596 User's Manual BUS REQUEST This signal when configured to an externally activated mode is used to trigger the bus throttle timers PORT When this signal is received the 82596 latches the data on the data bus into an internal 32-bit register When the CPU is asserting this signal it can write into the 82596 (via the data bus) This pin must be activated twice during all CPU Port access commands RESET This active high internally synchronized signal causes the 82596 to terminate current activity The signal must be high for at least five system clock cycles After five system clock cycles and four TxC clock cycles the 82596 will execute a Reset when it receives a high RESET signal When RESET returns to low the 82596 waits for the first CA signal and then begins the initialization sequence LITTLE ENDIAN BIG ENDIAN This dual-function pin is used to select byte ordering When LE BE is high little endian byte ordering is used when low big endian byte ordering is used for data in frames (bytes) and for control (SCB RFD CBL etc) CHANNEL ATTENTION The CPU uses this pin to force the 82596 to begin executing memory resident Command blocks The CA signal is internally synchronized The signal must be high for at least one system clock It is latched internally on the high to low edge and then detected by the 82596 The first CA after a Reset forces the 82596 into the initialization sequence beginning at location 00FFFFF6h or an SCP address written to the 82596 using CPU Port access All subsequent CA signals cause the 82596 to begin executing new command sequences from the SCB INTERRUPT A high signal on this pin notifies the CPU that the 82596 is requesting an interrupt This signal is an edge triggered interrupt signal and can be configured to be active high or low HOLD 123 O HLDA 118 I BREQ PORT 115 3 I I RESET 69 I LE BE 65 I CA 119 I INT INT 125 O 9 82596CA PIN DESCRIPTIONS (Continued) Symbol VCC VSS TxD TxC PQFP Pin No 17 Pins 17 Pins 54 64 O I Type POWER a 5 V g10% GROUND 0 V TRANSMIT DATA This pin transmits data to the serial link It is high when not transmitting TRANSMIT CLOCK This signal provides the fundamental timing for the serial subsystem The clock is also used to transmit data synchronously on the TxD pin For NRZ encoding data is transferred to the TxD pin on the high to low clock transition For Manchester encoding the transmitted bit center is aligned with the low to high transition Transmit clock must always be running for proper device operation LOOPBACK This TTL-level control signal enables the loopback mode In this mode serial data on the TxD input is routed through the 82C501 internal circuits and back to the RxD output without driving the transceiver cable To enable this signal both internal and external loopback need to be set with the Configure command RECEIVE DATA This pin receives NRZ serial data only It must be high when not receiving RECEIVE CLOCK This signal provides timing information to the internal shifting logic For NRZ data the state of the RxD pin is sampled on the high to low transition of the clock REQUEST TO SEND When this signal is low the 82596 informs the external interface that it has data to transmit It is forced high after a Reset or when transmission is stopped CLEAR TO SEND An active-low signal that enables the 82596 to send data It is normally used as an interface handshake to RTS Asserting CTS high stops transmission CTS is internally synchronized If CTS goes inactive meeting the setup time to the TxC negative edge the transmission will stop and RTS will go inactive within at most two TxC cycles CARRIER SENSE This signal is active low it is used to notify the 82596 that traffic is on the serial link It is only used if the 82596 is configured for external Carrier Sense In this configuration external circuitry is required for detecting traffic on the serial link CRS is internally synchronized To be accepted the signal must remain active for at least two serial clock cycles (for CRSF e 0) COLLISION DETECT This active-low signal informs the 82596 that a collision has occurred It is only used if the 82596 is configured for external Collision Detect External circuitry is required for collision detection CDT is internally synchronized To be accepted the signal must remain active for at least two serial clock cycles (for CDTF e 0) Name and Function LPBK 58 O RxD RxC 60 59 I I RTS 57 O CTS 62 I CRS 63 I CDT 61 I 10 82596CA 82596 AND HOST CPU INTERACTION The 82596CA and the host CPU communicate through shared memory Because of its on-chip DMA capability the 82596 can make data block transfers (buffers and frames) independently of the CPU this greatly reduces the CPU byte transfer overhead The 82596 is a multitasking coprocessor that comprises two independent logical units the Command Unit (CU) and the Receive Unit (RU) The CU executes commands from shared memory The RU handles all activities related to frame reception The independence of the CU and RU enables the 82596 to engage in both activities simultaneously the CU can fetch and execute commands from memory while the RU is storing received frames in memory The CPU is only involved with this process after the CU has executed a sequence of commands or the RU has finished storing a sequence of frames The CPU and the 82596 use the hardware signals Interrupt (INT) and Channel Attention (CA) to initiate communication with the System Control Block (SCB) see Figure 4 The 82596 uses INT to alert the CPU of a change in the contents of the SCB the CPU uses CA to alert the 82596 The 82596 has a CPU Port Access state that allows the CPU to execute certain functions without accessing memory The 82596 PORT pin and data bus pins are used to enable this feature The CPU can directly activate four operations when the 82596 is in this state 82596 BUS INTERFACE The 82596CA has bus interface timings and pin definitions that are compatible with Intel's 32-bit i486 TM SX and i486 TM DX microprocessors This eliminates the need for additional bus interface logic Operating at 33 MHz the 82596's bus bandwidth can be as high as 106 MB s Since Ethernet only requires 1 25 MB s this leaves a considerable amount of bandwidth for the CPU The 82596 also has a bus throttle to regulate its use of the bus Two timers can be programmed through the SCB one controls the maximum time the 82596 can remain on the bus the other controls the time the 82596 must stay off the bus (see Figure 5) The bus throttle can be programmed to trigger internally with HLDA or externally with BREQ These timers can restrict the 82596 HOLD activation time and improve bus utilization 82596 MEMORY ADDRESSING The 82596 has a 32-bit memory address range which allows addressing up to four gigabytes of memory The 82596 has three memory addressing modes (see Table 1) 82586 Mode The 82596 has a 24-bit memory address range The System Control Block Command List Receive Descriptor List and Buffer Descriptors must reside in one 64-KB memory segment Transmit and Receive buffers can reside in a 24-bit address space 32-Bit Segmented Mode The 82596 has a 32bit memory address range The System Control Block Command List Receive Descriptor List and Buffer Descriptors must reside in one 64-KB memory segment Transmit and Receive buffers can reside in a 32-bit address space Write an alternative System Configuration Pointer (SCP) This can be used when the 82596 cannot use the default SCP address space Write a different Dump Command Pointer and execute Dump This can be used for troubleshooting No Response problems Linear Mode The 82596 has a 32-bit memory address range Any memory structure can reside anywhere within the 32-bit memory address range The CPU can reset the 82596 via software without disturbing the rest of the system A self-test can be used for board testing the 82596 will execute a self-test and write the results to memory 11 82596CA 290218 - 4 Figure 4 82596 and Host CPU Intervention 290218 - 5 Figure 5 Bus Throttle Timers Table 1 82596 Memory Addressing Formats Operation Mode Pointer or Offset ISCP Address SCB Address Command Block Pointers Rx Frame Descriptors Tx Frame Descriptors Rx Buffer Descriptors Tx Buffer Descriptors Rx Buffers Tx Buffers 82586 24-Bit Linear Base (24) a Offset (16) Base (24) a Offset (16) Base (24) a Offset (16) Base (24) a Offset (16) Base (24) a Offset (16) Base (24) a Offset (16) 24-Bit Linear 24-Bit Linear 32-Bit Segmented 32-Bit Linear Base (32) a Offset (16) Base (32) a Offset (16) Base (32) a Offset (16) Base (32) a Offset (16) Base (32) a Offset (16) Base (32) a Offset (16) 32-Bit Linear 32-Bit Linear Linear 32-Bit Linear 32-Bit Linear 32-Bit Linear 32-Bit Linear 32-Bit Linear 32-Bit Linear 32-Bit Linear 32-Bit Linear 32-Bit Linear 12 82596CA 290218 - 6 Figure 6 82596 Shared Memory Structure 82596 SYSTEM MEMORY STRUCTURE The Shared Memory structure consists of four parts the Initialization Root the System Control Block the Command List and the Receive Frame Area (see Figure 6) The Initialization Root is in an established location known to the host CPU and the 82596 (00FFFFF6h) However the CPU can establish the Initialization Root in another location by using the CPU Port access This root is accessed during initialization and points to the System Control Block The System Control Block serves as a bidirectional mail drop for the host CPU and the 82596 CU and RU It is the central point through which the CPU and the 82596 exchange control and status information The SCB has two areas The first contains instructions from the CPU to the 82596 These include control of the CU and RU (Start Abort Suspend and Resume) a pointer to the list of CU commands a pointer to the Receive Frame Area a set of Interrupt Acknowledge bits and the T-ON and T-OFF timers for the bus throttle The second area contains status information the 82596 is sending to the CPU Such as the CU and RU states (Idle Active 13 82596CA Ready Suspended No Receive Resources etc ) interrupt bits (Command Completed Frame Received CU Not Ready and RU Not Ready) and statistical counters The Command List functions as a program for the CU individual commands are placed in memory units called Command Blocks (CBs) These CBs contain the parameters and status of specific highlevel commands called Action Commands e g Transmit or Configure Transmit causes the 82596 to transmit a frame The Transmit CB contains the destination address the length field and a pointer to a list of linked buffers holding the frame that is to be constructed from several buffers scattered throughout memory The Command Unit operates without CPU intervention the DMA for each buffer and the prefetching of references to new buffers is performed in parallel The CPU is notified only after a transmission is complete The Receive Frame Area is a list of Free Frame Descriptors (descriptors not yet used) and a list of userprepared buffers Frames arrive at the 82596 unsolicited the 82596 must always be ready to receive and store them in the Free Frame Area The Receive Unit fills the buffers when it receives frames and reformats the Free Buffer List into receivedframe structures The frame structure is for all practical purposes identical to the format of the frame to be transmitted The first Frame descriptor is referenced by the SCB Unless the 82596 is configured to Save Bad Frames the frame descriptor and the associated buffer descriptor which is wasted when a bad frame is received are automatically reclaimed and returned to the Free Buffer List Receive buffer chaining (storing incoming frames in a linked buffer list) significantly improves memory utilization Without buffer chaining the user must allocate consecutive blocks of memory each capable of containing a maximum frame (for Ethernet 1518 bytes) Since an average frame is about 200 bytes this is very inefficient With buffer chaining the user can allocate small buffers and the 82596 will only use those that are needed Figure 7 A-D illustrates how the 82596 uses the Receive Frame Area Figure 7A shows an unused Receive Frame Area composed of Free Frame Descriptors and Free Receive Buffers prepared by the user The SCB points to the first Frame Descriptor of the Frame Descriptor List Figure 7B shows the same Receive Frame Area after receiving one frame This first frame occupies two Receive Buffers and one Frame Descriptor a valid received frame will only occupy one Frame Descriptor After receiving this frame the 82596 sets the next Free Frame Descriptor RBD pointer to the next Free RBD Figure 7C shows the RFA after receiving a second frame In this example the second frame occupies only one Receive Buffer and one RFD The 82596 again sets the RBD pointer This process is repeated again in Figure 7D showing the reception of another frame using one Receive Buffer in this example there is an extra Frame Descriptor TRANSMIT AND RECEIVE MEMORY STRUCTURES There are three memory structures for reception and transmission The 82586 memory structure the Flexible memory structure and the Simplified memory structure The 82586 mode is selected by configuring the 82596 during initialization In this mode all the 82596 memory structures are compatible with the 82586 memory structures When the 82596 is not configured to the 82586 mode the other two memory structures Simplified and Flexible are available for transmitting and receiving These structures are selected by setting the S F bit in the Transmit Command and or the Receive Frame Descriptor (see Figures 29 30 41 and 42) It is recommended that any linked list of buffers be relegated to a single type either simplified or flexible The Simplified memory structure offers a simple structure for ease of programming (see Figure 8) All information about a frame is contained in one structure for example during reception the RFD and data field are contained in one structure The Flexible memory structure (see Figure 9) has a control field that allows the programmer to specify the amount of receive data the RFD will contain for receive operations and the amount of transmit data the Transmit Command Block will contain for transmit operations For example when the control field in the RFD is set to 20 bytes during a reception the first 20 bytes of the data field are stored in the RFD (6 bytes of destination address 6 bytes of source address 2 bytes of length field and 6 bytes of data) and the remainder of the data field is stored in the Receive Data Buffers This is useful for capturing frame headers when header information is contained in the data field The header information can then be automatically stored in the RFD partitioned from the Receive Data Buffer The control field can also be used for the Transmit Command when the Flexible memory structure is used The quantity of data field bytes to be transmitted from the Transmit Command Block is specified by the variable control field 14 82596CA 290218 - 7 Figure 7 Frame Reception in the RFA 15 82596CA 290218 - 8 Figure 8 Simplified Memory Structure 290218 - 9 Figure 9 Flexible Memory Structure 16 82596CA start frame delimiter is 10101011 and the end frame delimiter is indicated by the lack of a signal after the last bit of the frame check sequence field has been transmitted In EOC the 82596 can be configured to extend short frames by adding pad bytes (7Eh) during transmission according to the length field When a collision occurs the 82596 manages the jam random wait and retry processes reinitializing DMA pointers without CPU intervention Multiple frames can be sent by linking the appropriate number of Transmit commands together This is particularly useful when transmitting a message larger than the maximum frame size (1518 bytes for Ethernet) TRANSMITTING FRAMES The 82596 executes high-level Action Commands from the Command List in system memory Action Commands are fetched and executed in parallel with the host CPU operation thereby significantly improving system performance The format of the Action Commands is shown in Figure 10 Figure 28 shows the 82586 mode and Figures 29 and 30 show the command formats of the Linear and 32-bit Segmented modes A single Transmit command contains as part of the command-specific parameters the destination address and length field of the transmitted frame and a pointer to buffer area in memory containing the data portion of the frame The data field is contained in a memory data structure consisting of a buffer descriptor (BD) and a data buffer or a linked list of buffer descriptors and buffers as shown in Figure 11 Multiple data buffers can be chained together using the BDs Thus a frame with a long data field can be transmitted using several (shorter) data buffers chained together This chaining technique allows the system designer to develop efficient buffer management The 82596 automatically generates the preamble (alternating 1s and 0s) and start frame delimiter fetches the destination address and length field from the Transmit command inserts its unique address as the source address fetches the data field specified by the Transmit command and computes and appends the CRC to the end of the frame (see Figure 12) In the Linear and 32-bit Segmented mode the CRC can be optionally inserted on a frame-byframe basis by setting the NC bit in the Transmit Command Block (see Figures 29 and 30) The 82596 generates the standard End Of Carrier (EOC) start and end frame delimiters In EOC the START FRAME DELIMITER DESTINATION ADDRESS SOURCE ADDRESS 290218 - 10 Figure 10 Action Command Format 290218 - 11 Figure 11 Data Buffer Descriptor and Data Buffer Structure PREAMBLE LENGTH FIELD DATA FIELD FRAME CHECK SEQUENCE END FRAME DELIMITER Figure 12 Frame Format 17 82596CA RECEIVING FRAMES To reduce CPU overhead the 82596 is designed to receive frames without CPU supervision The host CPU first sets aside an adequate receive buffer space and then enables the 82596 Receive Unit Once enabled the RU watches for arriving frames and automatically stores them in the Receive Frame Area (RFA) The RFA contains Receive Frame Descriptors Receive Buffer Descriptors and Data Buffers (see Figure 13) The individual Receive Frame Descriptors make up a Receive Descriptor List (RDL) used by the 82596 to store the destination and source addresses the length field and the status of each frame received (see Figure 14) Once enabled the 82596 checks each passing frame for an address match The 82596 will recognize its own unique address one or more multicast addresses or the broadcast address If a match is found the 82596 stores the destination and source addresses and the length field in the next available RFD It then begins filling the next available Data Buffer on the FBL which is pointed to by the current RFD with the data portion of the incoming frame As one Data Buffer is filled the 82596 automatically fetches the next DB on the FBL until the entire frame is received This buffer chaining technique is particularly memory efficient because it allows the system designer to set aside buffers to fit frames much shorter than the maximum allowable frame length If AL-LOC e 1 or if the flexible memory structure is used the addresses and length field can be placed in the Receive Buffer Once the entire frame is received without error the 82596 does the following housekeeping tasks frame The 82596 will continue to receive frames without CPU help as long as Receive Frame Descriptors and Data Buffers are available 82596 NETWORK MANAGEMENT AND DIAGNOSTICS The behavior of data communication networks is normally very complex because of their distributed and asynchronous nature It is particularly difficult to pinpoint a failure when it occurs The 82596 has extensive diagnostic and network management functions that help improve reliability and testability The 82596 reports on the following events after each frame is transmitted Transmission successful Transmission unsuccessful Lost Carrier Sense Transmission unsuccessful Lost Clear to Send Transmission unsuccessful A DMA underrun occurred because the system bus did not keep up with the transmission Transmission unsuccessful The number of collisions exceeded the maximum allowed Number of Collisions The number of collisions experienced during transmission of the frame Heartbeat Indicator This indicates the presence of a heartbeat during the last Interframe Spacing (IFS) after transmission When configured to Save Bad Frames the 82596 checks each incoming frame and reports the following errors CRC error Incorrect CRC in a properly aligned frame The actual count field of the last Buffer Descriptor used to hold the frame just received is updated with the number of bytes stored in the associated Data Buffer Alignment error Incorrect CRC in a misaligned frame Frame too short The frame is shorter than the value configured for minimum frame length The next available Receive Frame Descriptor is fetched Overrun Part of the frame was not placed in memory because the system bus did not keep up with incoming data The address of the next available Buffer Descriptor is written to the next available Receive Frame Descriptor A frame received interrupt status bit is posted in the SCB Out of buffer Part of the frame was discarded because of insufficient memory storage space Receive collision A collision was detected during reception and the destination address of the incoming frame matches the 82596 individual address Collisions in the preamble are not counted An interrupt is sent to the CPU If a frame error occurs for example a CRC error the 82596 automatically reinitializes its DMA pointers and reclaims any data buffers containing the bad Length error A frame not matching the frame length parameter was detected 18 82596CA 290218 - 12 Figure 13 Receive Frame Area Diagram 290218 - 13 Figure 14 Receive Frame Descriptor 19 82596CA The 82596 will receive all frames and put them in the RFD Frames that exceed the available space in the RFD will be truncated the status will be updated and the 82596 will retrieve the next RFD This allows the user to capture the initial data bytes of each frame (for instance the header) and discard the remainder of the frame The 82596 also has a monitor mode for network analysis During normal operation the receive function enables the 82596 to receive frames that pass address filtering These frames must have the Start of Frame Delimiter (SFD) field and must be longer than the absolute minimum frame length of 5 bytes (6 bytes in case of Multicast address filtering) Contents and status of the received frames are transferred to memory The monitor function enables the 82596 to simply evaluate the incoming frames The 82596 can monitor the frames that pass or do not pass the address filtering It can also monitor frames which do not have the SFD fields The 82596 can be configured to only keep statistical information about monitor frames Three options are available in the Monitor mode These options are selected by the two monitor mode configuration bits available in the configuration command When the first option is selected the 82596 receives good frames that pass address filtering and transfers them to memory while monitoring frames that do not pass address filtering or are shorter than the minimum frame size (these frames are not transferred to memory) When this option is used the 82596 updates six counters CRC errors alignment errors no resource errors overrun errors short frames and total good frames received When the second option is selected the receive function is completely disabled The 82596 monitors only those frames that pass address filterings and meet the minimum frame length requirement When this option is used the 82596 updates six counters CRC errors alignment errors total frames (good and bad) short frames collisions detected and total good frames When the third option is selected the receive function is completely disabled The 82596 monitors all frames including frames that do not have a Start Frame Delimiter When this option is used the 82596 updates six counters CRC errors alignment errors total frames (good and bad) short frames collisions detected and total good frames NETWORK PLANNING AND MAINTENANCE To properly plan operate and maintain a communication network the network management entity must accumulate information on network behavior The 82596 provides a rich set of network-wide diagnostics that can serve as the basis for a network management entity Information on network activity is provided in the status of each frame transmitted The 82596 reports the following activity indicators after each frame Number of collisions The number of collisions the 82596 experienced while attempting to transmit the frame Deferred transmission During the first transmission attempt the 82596 had to defer to traffic on the link The 82596 updates its 32-bit statistical counters after each received frame that both passes address filtering and is longer than the Minimum Frame Length configuration parameter The 82596 reports the following statistics CRC errors The number of well-aligned frames that experienced a CRC error Alignment errors The number of misaligned frames that experienced a CRC error No resources The number of frames that were discarded because of insufficient resources for reception Overrun errors The number of frames that were not completely stored in memory because the system bus did not keep up with incoming data Receive Collision counter The number of collisions detected during receive Collisions occurring before the minimum frame length will be counted as short frames Collisions in the preamble will not be counted at all Short Frame counter The number of frames that were discarded because they were shorter than the configured minimum frame length Once again these counters are not updated until the 82596 decodes a destination address match The 82596 can be configured to Promiscuous mode In this mode it captures all frames transmitted on the network without checking the Destination Address This is useful when implementing a monitoring station to capture all frames for analysis A useful method of capturing frame headers is to use the Simplified memory mode configure the 82596 to Save Bad Frames and configure the 82596 to Promiscuous mode with space in the RFD allocated for specific number of receive data bytes 20 82596CA STATION DIAGNOSTICS AND SELF-TEST The 82596 provides a large set of diagnostic and network management functions These include internal and external loopback and time domain reflectometry for locating fault points in the network cable The 82596 ensures software reliability by dumping the contents of the 82596 internal registers into system memory The 82596 has a self-test mode that enables it to run an internal self-test and place the results in system memory INITIALIZING THE 82596 A Reset command is issued to the 82596 to prepare it for normal operation The 82596 is initialized through two data structures that are addressed by two pointers the System Configuration Pointer (SCP) and the Intermediate System Configuration Pointer (ISCP) The initialization procedure begins when a Channel Attention signal is asserted after RESET The 82596 uses the address of the double word that contains the SCP as a default 00FFFFF4h Before the CA signal is asserted this default address can be changed to any other available address by asserting the PORT pin and providing the desired address over the D31 -D4 pins of the address bus Pins D3 -D0 must be 0010 i e any alternative address must be aligned to 16-byte boundaries All addresses sent to the 82596 must be word aligned which means that all pointers and memory structures must start on an even address (A0 e zero) 82586 SOFTWARE COMPATIBILITY The 82596 has a software-compatible state in which all its memory structures are compatible with the 82586 memory structure This includes all the Action Commands the Receive Frame Area (including the RFD Buffer Descriptors and Data Buffers) the System Control Block and the initialization procedures There are two minor differences between the 82596 in the 82586-Compatible memory structure and the 82586 SYSTEM CONFIGURATION POINTER (SCP) The SCP contains the sysbus byte and the location of the next structure of the initialization process the ISCP The following parameters are selected in the SYSBUS When the internal and external loopback bits in the Configure command are set to 11 the 82596 is in external loopback and the LPBK pin is activated in the 82586 this situation would produce internal loopback During a Dump command both the 82596 and 82586 dump the same number of bytes however the data format is different The 82596 operation mode The Bus Throttle timer triggering method Lock enabled Interrupt polarity Big Endian 32-bit entity mode Byte ordering is determined by the LE BE pin LE BE e 1 selects Little Endian byte ordering and LE BE e 0 selects Big Endian byte ordering NOTE In the following X indicates a bit not checked 82586 mode This bit must be set to 0 in all other modes 21 82596CA The following diagram illustrates the format of the SCP 31 ODD WORD SYSBUS 16 15 EVEN WORD 0 XXXXXXXX A31 A31 X A24 A23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FFFFF4h ISCP ADDRESS A0 0FFFFFCh X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0FFFFF8h A24 are not checked in 82586 mode X areas are not checked in 82586 mode they must be 0 in all other modes 290218 - 14 ISCP ADDRESS The physical address of the ISCP In the 82586 mode bits A31 - A24 are considered to be zero Figure 15 The System Configuration Pointer Writing the Sysbus When writing the sysbus byte it is important to pay attention to the byte order When a Little Endian processor is used the sysbus byte is located at byte address 00FFFFF6h (or address n a 2 if an alternative SCP address n was programmed) When a processor using Big Endian byte ordering is used the sysbus alternative SCP and ISCP addresses will be different The sysbus byte is located at 00FFFFF5h If an alternative SCP address is programmed the sysbus byte should be at byte address n a 1 22 82596CA INTERMEDIATE SYSTEM CONFIGURATION POINTER (ISCP) The ISCP indicates the location of the System Control Block Often the SCP is in ROM and the ISCP is in RAM The CPU loads the SCB address (or an equivalent data structure) into the ISCP and asserts CA This Channel Attention signal causes the 82596 to begin its initialization procedure and to get the SCB address from the ISCP and SCP In 82586 and 32-bit Segmented modes the SCP base address is also the base address of all Command Blocks Frame Descriptors and Buffer Descriptors (but not buffers) All these data structures must reside in one 64-KB segment however in Linear mode no such limitation is imposed The following diagram illustrates the ISCP format ODD WORD 31 A15 SCB OFFSET A23 XXXXXXXX A31 A24 16 15 A0 SCB BASE ADDRESS EVEN WORD 87 BUSY 0 ISCP A0 ISCP a 4 u in 82586 mode in 32-bit segmented mode BUSY SCB OFFSET SCB BASE Indicates that the 82596 is being initialized The CPU sets the ISCP to 01h before it gives the first CA to the 82596 The ISCP is cleared by the 82596 after the SCB base and offset are read Note that the most significant byte of the first word of the ISCP is not modified when BUSY is cleared This 16-bit quantity specifies the offset portion of the address of the SCB Specifies the base portion of the address of the SCB The base of SCB is also the base of all 82596 Command Blocks Frame Descriptors and Buffer Descriptors In the 82586 mode bits A31-A24 are considered to be zero 82586 and 32-Bit Segmented Modes EVEN WORD 87 000 SCB ABSOLUTE ADDRESS BUSY Figure 16 The Intermediate System Configuration Pointer ODD WORD 31 000 A31 16 15 0 ISCP A0 ISCP a 4 BUSY SCB ADDRESS Indicates that the 82596 is being initialized The ISCP is set to 01h by the CPU before its first CA to the 82596 It is cleared by the 82596 after the SCB address is read This 32-bit quantity specifies the physical address of the SCB Linear Mode Figure 17 The Intermediate System Configuration Pointer INITIALIZATION PROCESS The CPU sets up the SCP ISCP and the SCB structures and if desired an alternative SCP address It also sets BUSY to 01h The 82596 is initialized when a Channel Attention signal follows a Reset signal causing the 82596 to access the System Configuration Pointer The sysbus byte the operational mode the bus throttle timer triggering method the interrupt polarity and the state of LOCK are read After reset the Bus Throttle timers are essentially disabled the T-ON value is infinite the T-OFF value is zero After the SCP is read the 82596 reads the ISCP and saves the SCB address In 82586 and 32-bit Segmented modes this address is represented as a base address plus the offset (this base address is also the base address of all the control blocks) In Linear mode the base address is also an absolute address The 82596 clears BUSY sets CX and CNR to equal 1 in the SCB clears the SCB command word sends an interrupt to the CPU and awaits another Channel Attention signal RESET configures the 82596 to its default state before CA is asserted 23 82596CA CONTROLLING THE 82596CA The host CPU controls the 82596 with the commands data structures and methods described in this section The CPU and the 82596 communicate through shared memory structures The 82596 contains two independent units the Command Unit and the Receive Unit The Command Unit executes commands from the CPU and the Receive Unit handles frame reception These two units are controlled and monitored by the CPU through a shared memory structure called the System Control Block (SCB) The CPU and the 82596 use the CA and INT signals to communicate with the SCB 82596 CPU ACCESS INTERFACE (PORT) The 82596 has a CPU access interface that allows the host CPU to do four things Write an alternative System Configuration Pointer address Write an alternative Dump area pointer and perform Dump Execute a software reset Execute a self-test The following events initiate the CPU access state Presence of an address on the D31 -D4 data bus pins The D3 -D0 pins are used to select one of the four functions The PORT input pin is asserted as in a regular write cycle NOTE The SCP Dump and Self-Test addresses must be 16-byte aligned The 82596 requires two 16-bit write cycles for a port command The first write holds the internal machines and reads the first 16 bits the second activates the PORT command and reads the second 16 bits The PORT Reset is useful when only the 82596 needs to be reset The CPU must wait for 10-system and 5-serial clocks before issuing another CA to the 82596 this new CA begins a new initialization process The Dump function is useful for troubleshooting No Response problems If the chip is in a No Response state the PORT Dump operation can be executed and a PORT Reset can be used to reinitialize the 82596 without disturbing the rest of the system The Self-Test function can be used for board testing the 82596 will execute a self-test and write the results to memory Table 2 PORT Function Selection D31 Function Reset Self-Test SCP Dump A31 A31 A31 A31 Addresses and Results Don't Care Self-Test Results Address Alternative SCP Address Dump Area Pointer A4 A4 A4 A4 D4 D3 0 0 0 0 D2 0 0 0 0 D1 0 0 1 1 D0 D0 0 1 0 1 MEMORY ADDRESSING FORMATS The 82596 accesses memory by 32-bit addresses There are two types of 32-bit addresses linear and segmented The type of address used depends on the 82596 operating mode and the type of memory structure it is addressing The 82596 has three operating modes 24 82596CA 82586 Mode A Linear address is a single 24-bit entity Address pins A31 -A24 are always zero A Segmented address uses a 24-bit base and a 16-bit offset 32-bit Segmented Mode A Linear address is a single 32-bit entity A Segmented address uses a 32-bit base and a 16-bit offset NOTE In the previous two memory addressing modes each command header (CB TBD RFD RBD and SCB) must wholly reside within one segment If the 82596 encounters a memory structure that does not follow this restriction the 82596 will fetch the next contiguous location in memory (beyond the segment) Linear Mode A Linear address is a single 32-bit entity There are no Segmented addresses Linear addresses are primarily used to address transmit and receive data buffers In the 82586 and 32-bit Segmented modes segmented addresses (base plus offset) are used for all Command Blocks Buffer Descriptors Frame Descriptors and System Control Blocks When using Segmented addresses only the offset portion of the entity being addressed is specified in the block The base for all offsets is the same that of the SCB See Table 1 LITTLE ENDIAN AND BIG ENDIAN BYTE ORDERING The 82596 supports both Little Endian and Big Endian byte ordering for its memory structures The 82596 A1 stepping supports Big Endian byte ordering for word and byte entities Dword entities are not supported with 82596 A1 Big Endian byte ordering This results in slightly different 82596A1 memory structures for Big Endian operation These structures are defined in the 32-Bit LAN Components User's Manual The 82596 B stepping supports Big Endian byte ordering for Linear mode only All 82596 B 32-bit address pointers are treated as 32-bit Big Endian entities however the SCB absolute address and statistical counters are treated as two 16-bit Big Endian entities This 32-bit Big Endian entity support is configured through bit 7 in the SYSBUS byte The 82596 C-step has a New Enhanced Big Endian Mode where in Linear Addressing mode true 32-bit Big Endian functionality is achieved New Enhanced Big Endian Mode is enabled exactly the same as the B-step by setting bit 7 of the SYSBUS byte This mode is software compatible with the big endian mode of the B-step with one exception no 32-bit addresses need to be swapped by software in the C-step In this new mode the 82596 C-step treats 32-bit address pointers as true 32-bit entities and the SCB absolute address and statistical counters are still treated as two 16-bit big endian entities Not setting this mode will configure the 82596 C-step to be 100% compatible to the A1-step big endian mode NOTE All 82596 memory entities must be word or dword aligned except the transmit buffers can be byte aligned for the 82596 B or C-steppings An example of a dword entity is a frame descriptor command status dword whereas the raw data of the frame are byte entities Both 32- and 16-bit buses are supported When a 16-bit bus is used with Big Endian memory organization data lines D15 -D0 are used The 82596 has an internal crossover that handles these swap operations 25 82596CA COMMAND UNIT (CU) The Command Unit is the logical unit that executes Action Commands from a list of commands very similar to a CPU program A Command Block is associated with each Action Command The CU is modeled as a logical machine that takes at any given time one of the following states Idle The CU is not executing a command and is not associated with a CB on the list This is the initial state Suspended The CU is not executing a command however it is associated with a CB on the list Active The CU is executing an Action Command and pointing to its CB The CPU can affect CU operation in two ways by issuing a CU Control Command or by setting bits in the Command word of the Action Command When programming the 82596 CU it is important to consider the asynchronous way the 82596 processes commands If a command is issued to the 82596 CU it may be busy processing other commands In order to avoid asynchronous race conditions the following guidelines are recommended to the 82596 programmer If the CU is already in the Active state and another command needs to be executed it is unwise to immediately issue another CU Start command If a new command (or list of commands) needs to be started first issue a CU Suspend command wait for the CU to become Suspended then issue the new CU Start This will insure that all commands are processed correctly In general it is a good idea to make sure any CU command has been accepted and executed before issuing a new control command to the CU RECEIVE UNIT (RU) The Receive Unit is the logical unit that receives frames and stores them in memory The RU is modeled as a logical machine that takes at any given time one of the following states Idle The RU has no memory resources and is discarding incoming frames This is the initial state No Resources The RU has no memory resources and is discarding incoming frames This state differs from Idle in that the RU accumulates statistics on the number of discarded frames Suspended The RU has memory available for storing frames but is discarding them The suspend state can only be reached if the CPU forces this through the SCB or sets the suspend bit in the RFD Ready The RU has memory available and is storing incoming frames The CPU can affect RU operation in three ways by issuing an RU Control Command by setting bits in the Frame Descriptor Command word of the frame being received or by setting the EL bit of the current buffer's Buffer Descriptor When programming the 82596 RU it is important to consider the asynchronous way the 82596 processes receive frames If an RU Start is issued to the 82596 RU it may be busy processing other incoming packets In order to avoid asynchronous race conditions the following guidelines are recommended to the 82596 programmer If the RU is already in the Ready state and a new RFA is required to be started it is unwise to immediately issue another RU Start command If the new RFA needs to be started first issue an RU Suspend command wait for the RU to become Suspended then issue the new RU Start This will insure that all incoming frames are received correctly In general it is a good idea to make sure any RU command has been accepted and executed before issuing a new control command to the RU 26 82596CA SYSTEM CONTROL BLOCK (SCB) The SCB is a memory block that plays a major role in communications between the CPU and the 82596 Such communications include the following Commands issued by the CPU Status reported by the 82596 Control commands are sent to the 82596 by writing them into the SCB and then asserting CA The 82596 examines the command performs the required action and then clears the SCB command word Control commands perform the following types of tasks Operation of the Command Unit (CU) The SCB controls the CU by specifying the address of the Command Block List (CBL) and by starting suspending resuming or aborting execution of CBL commands Operation of the Bus Throttle The SCB controls the Bus Throttle timers by providing them with new values and sending the Load and Start timer commands The timers can be operated in both the 32-bit Segmented and Linear modes Reception of frames by the Receive Unit (RU) The SCB controls the RU by specifying the address of the Receive Frame Area and by starting suspending resuming or aborting frame reception Acknowledgment of events that cause interrupts Resetting the chip The 82596 sends status reports to the CPU via the System Control Block The SCB contains four types of status reports The cause of the current interrupts These interrupts are caused by one or more of the following 82596 events The Command Unit becomes inactive The Receive Unit becomes not ready The status of the Command Unit The status of the Receive Unit The Command Unit completes an Action Command that has its I bit set The Receive Unit receives a frame Status reports from the 82596 regarding reception of corrupted frames 27 82596CA Events can be cleared only by CPU acknowledgment If some events are not acknowledged by the ACK field the Interrupt signal (INT) will be reissued after Channel Attention (CA) is processed Furthermore if a new event occurs while an interrupt is set the interrupt is temporarily cleared to trigger edge-triggered interrupt controllers The CPU uses the Channel Attention line to cause the 82596 to examine the SCB This signal is trailing-edge triggered the 82596 latches CA on the trailing edge The latch is cleared by the 82596 before the SCB control command is read 31 ACK X ODD WORD CUC R RUC 16 15 XXXX STAT 0 EVEN WORD CUS 0 RUS 0 0 0 0 0 SCB SCB a 4 SCB a 8 SCB a 12 RFA OFFSET ALIGNMENT ERRORS OVERRUN ERRORS CBL OFFSET CRC ERRORS RESOURCE ERRORS Figure 18 SCB 31 ACK 0 ODD WORD CUC R RUC 16 15 0000 82586 Mode EVEN WORD 0 T 0 0 0 SCB SCB a 4 SCB a 8 SCB a 12 SCB a 16 SCB a 20 SCB a 24 SCB a 28 T-OFF TIMER SCB a 32 STAT 0 CUS RUS RFA OFFSET CRC ERRORS ALIGNMENT ERRORS RESOURCE ERRORS ( ) OVERRUN ERRORS ( ) RCVCDT ERRORS ( ) SHORT FRAME ERRORS T-ON TIMER In monitor mode these counters change function CBL OFFSET Figure 19 SCB 31 ACK 0 ODD WORD CUC R RUC 32-Bit Segmented Mode EVEN WORD STAT 0 CUS RUS 0 T 0 0 0 SCB SCB a 4 SCB a 8 SCB a 12 SCB a 16 SCB a 20 SCB a 24 SCB a 28 SCB a 32 T-OFF TIMER SCB a 36 16 15 0000 COMMAND BLOCK ADDRESS RECEIVE FRAME AREA ADDRESS CRC ERRORS ALIGNMENT ERRORS RESOURCE ERRORS ( ) OVERRUN ERRORS ( ) RCVCDT ERRORS ( ) SHORT FRAME ERRORS T-ON TIMER In MONITOR mode these counters change function Figure 20 SCB Linear Mode 28 82596CA Command Word 31 ACK 0 CUC R RUC 0 0 0 16 0 SCB a 2 These bits specify the action to be performed as a result of a CA This word is set by the CPU and cleared by the 82596 Defined bits are Bit 31 ACK-CX Bit 30 ACK-FR Bit 29 ACK-CNA Bit 28 ACK-RNR Bits 24-26 CUC Acknowledges that the CU completed an Action Command Acknowledges that the RU received a frame Acknowledges that the Command Unit became not active Acknowledges that the Receive Unit became not ready (3 bits) This field contains the command to the Command Unit Valid values are 0 NOP (does not affect current state of the unit) 1 Start execution of the first command on the CBL If a command is executing complete it before starting the new CBL The beginning of the CBL is in CBL OFFSET (address) Resume the operation of the Command Unit by executing the next command This operation assumes that the Command Unit has been previously suspended Suspend execution of commands on CBL after current command is complete Abort current command immediately Loads the Bus Throttle timers so they will be initialized with their new values after the active timer (T-ON or T-OFF) reaches Terminal Count If no timer is active new values will be loaded immediately This command is not valid in 82586 mode Loads and immediately restarts the Bus Throttle timers with their new values This command is not valid in 82586 mode Reserved 2 3 4 5 6 7 Bit 23 RESET Bits 20-22 RUC Reset chip (logically the same as hardware RESET) (3 bits) This field contains the command to the Receive Unit Valid values are 0 NOP (does not alter current state of unit) 1 Start reception of frames The beginning of the RFA is contained in the RFA OFFSET (address) If a frame is being received complete reception before starting 2 Resume frame reception (only when in suspended state) 3 4 5-7 Suspend frame reception If a frame is being received complete its reception before suspending Abort receiver operation immediately Reserved 29 82596CA Status Word 15 STAT 0 CUS 0 RUS 0 0 0 0 0 SCB 82586 mode 15 STAT 0 CUS RUS T 0 0 0 0 SCB 32-Bit Segmented and Linear mode Indicates the status of the 82596 This word is modified only by the 82596 Defined bits are Bit 15 CX Bit 14 FR Bit 13 CNA Bit 12 RNR Bits 8-10 CUS The CU finished executing a command with its I (interrupt) bit set The RU finished receiving a frame The Command Unit left the Active state The Receive Unit left the Ready state (3 bits) This field contains the status of the command unit Valid values are 0 Idle 1 2 3-7 Bits 4-7 RUS Suspended Active Not used This field contains the status of the receive unit Valid values are 0h (0000) Idle 1h (0001) Suspended 2h (0010) 4h (0100) Ah (1010) Ch (1100) No Resources This bit indicates both no resources due to lack of RFDs in the RDL and no resources due to lack of RBDs in the FBL Ready No resources due to no more RBDs (not in the 82586 mode) No more RBDs (not in 82586 mode) Bit 3 T No other combinations are allowed Bus Throttle timers loaded (not in 82586 mode) SCB OFFSET ADDRESSES CBL Offset (Address) In 82586 and 32-bit Segmented modes this 16-bit quantity indicates the offset portion of the address for the first Command Block on the CBL In Linear mode it is a 32-bit linear address for the first Command Block on the CBL It is accessed only if CUC equals Start RFA Offset (Address) In 82586 and 32-bit Segmented modes this 16-bit quantity indicates the offset portion of the address for the Receive Frame Area In Linear mode it is a 32-bit linear address for the Receive Frame Area It is accessed only if RUC equals Start 30 82596CA SCB STATISTICAL COUNTERS Statistical Counter Operation The CPU is responsible for clearing all error counters before initializing the 82596 The 82596 updates these counters by reading them adding 1 and then writing them back to the SCB The counters are wraparound counters After reaching FFFFFFFFh the counters wrap around to zero The 82596 updates the required counters for each frame It is possible for more than one counter to be updated multiple errors will result in all affected counters being updated The 82596 executes the read-counter increment write-counter operation without relinquishing the bus (locked operation) This is to ensure that no logical contention exists between the 82596 and the CPU due to both attempting to write to the counters simultaneously In the dual-port memory configuration the CPU should not execute any write operation to a counter if LOCK is asserted The counters are 32-bits wide and their behavior is fully compatible with the IEEE 802 3 standard The 82596 supports all relevant statistics (mandatory optional and desired) through the status of the transmit and receive header and directly through SCB statistics CRCERRS This 32-bit quantity contains the number of aligned frames discarded because of a CRC error This counter is updated if needed regardless of the RU state ALNERRS This 32-bit quantity contains the number of frames that both are misaligned (i e where CRS deasserts on a nonoctet boundary) and contain a CRC error The counter is updated if needed regardless of the RU state SHRTFRM This 32-bit quantity contains the number of received frames shorter than the minimum frame length The last three counters change function in monitor mode RSCERRS This 32-bit quantity contains the number of good frames discarded because there were no resources to contain them Frames intended for a host whose RU is in the No Receive Resources state fall into this category This counter is updated only if the RU is in the No Resources state When in Monitor mode this counter counts the total number of frames good and bad 31 82596CA OVRNERRS This 32-bit quantity contains the number of frames known to be lost because the local system bus was not available If the traffic problem lasts longer than the duration of one frame the frames that follow the first are lost without an indicator and they are not counted This counter is updated if needed regardless of the RU state This 32-bit counter contains the number of collisions detected during frame reception This counter will only be updated if at least 64 bytes of data are received before the collision occurs If a collision occurs before 64 bytes of data are received the frame is counted as a short frame If the collision occurs in the preamble no counters are incremented ACTION COMMANDS AND OPERATING MODES This section lists all the Action Commands of the Command Unit Command Block List (CBL) Each command contains the Command field the Status and Control fields the link to the next Action Command and any command-specific parameters There are three basic types of action commands 82596 Configuration and Setup Transmission and Diagnostics The following is a list of the actual commands NOP Individual Address Setup Configure MC Setup Transmit TDR Dump Diagnose The 82596 has three addressing modes In the 82586 mode all the Action Commands look exactly like those of the 82586 82586 Mode The 82596 software and memory structure is compatible with the 82586 32-Bit Segmented Mode The 82596 can access the entire system memory and use the two new memory structures Simplified and Flexible while still using the segmented approach This does not require any significant changes to existing software Linear Mode The 82596 operates in a flat linear 4 gigabyte memory space without segmentation It can also use the two new memory structures In the 32-bit Segmented mode there are some differences between the 82596 and 82586 action commands mainly in programming and activating new 82596 features Those bits marked ``don't care'' in the compatible mode are not checked however we strongly recommend that those bits all be zeroes this will allow future enchancements and extensions In the Linear mode all of the address offsets become 32-bit address pointers All new 82596 features are accessible in this mode and all bits previously marked ``don't care'' must be zeroes The Action Commands and all other 82596 memory structures must begin on even byte boundaries i e they must be word aligned 32 82596CA NOP This command results in no action by the 82596 except for those performed in the normal command processing It is used to manipulate the CBL manipulation The format of the NOP command is shown in Figure 21 NOP 31 EL S X X I X X X X X X X ODD WORD X X X X X X X X X X X X X X 0 X 0 X 82586 and 32-Bit Segmented Modes 16 15 0 C B OK 0 0 0 X A15 EVEN WORD 0 0 0 0 0 0 0 0 0 LINK OFFSET 0 00 A0 4 NOP 31 EL S A31 I 0 0 0 ODD WORD 0 0 0 0 0 0 0 0 0 Linear Mode 16 15 0 C B OK 0 0 0 EVEN WORD 0 0 0 0 0 0 0 0 0 0 00 A0 4 LINK ADDRESS Figure 21 where LINK POINTER EL S I CMD (bits 16-18) Bits 19-28 C In the 82586 or 32-bit Segmented modes this is a 16-bit offset to the next Command Block In the Linear mode this is the 32-bit address of the next Command Block If set this bit indicates that this command block is the last on the CBL If set to one suspend the CU upon completion of this CB If set to one the 82596 will generate an interrupt after execution of the command is complete If I is not set to one the CX bit will not be set The NOP command Value 0h Reserved (zero in the 32-bit Segmented and Linear modes) This bit indicates the execution status of the command The CPU initially resets it to zero when the Command Block is placed on the CBL Following a command Completion the 82596 will set it to one This bit indicates that the 82596 is currently executing the NOP command It is initially reset to zero by the CPU The 82596 sets it to one when execution begins and to zero when execution is completed This bit is also set when the 82596 prefetches the command NOTE B The C and B bits are modified in one operation OK Indicates that the command was executed without error If set to one no error occurred (command executed OK) If zero an error occured Individual Address Setup This command is used to load the 82596 with the Individual Address This address is used by the 82596 for inserting the Source Address during transmission and recognizing the Destination Address during reception After RESET and prior to Individual Address Setup Command execution the 82596 assumes the Broadcast Address is the Individual Address in all aspects i e This will be the Individual Address Match reference This will be the Source Address of a transmitted frame (for AL-LOC e 0 mode only) 33 82596CA The format of the Individual Address Setup command is shown in Figure 22 IA Setup 31 EL S I X X X ODD WORD X X X X X X X 0 0 82586 and 32-Bit Segmented Modes 16 15 1 C B OK A 0 1st byte A15 EVEN WORD 0 0 0 0 0 0 0 0 0 0 LINK OFFSET 4th byte 3rd byte 0 00 A0 4 8 INDIVIDUAL ADDRESS 6th byte 5th byte IA Setup 31 EL S A31 4th byte 3rd byte I 0 0 0 ODD WORD 0 0 0 0 0 0 0 0 0 1 Linear Mode EVEN WORD 0 0 0 0 0 0 0 0 0 0 0 0 00 A0 4 1st byte 5th byte 8 C 6th byte C B OK A 16 15 LINK ADDRESS INDIVIDUAL ADDRESS Figure 22 where LINK ADDRESS EL B C I S A As per standard Command Block (see the NOP command for details) Indicates that the command was abnormally terminated due to CU Abort control command If one then the command was aborted and if necessary it should be repeated If this bit is zero the command was not aborted Reserved (zero in the 32-bit Segmented and Linear modes) The Address Setup command Value 1h The individual address of the node 0 to 6 bytes long Bits 19-28 CMD (bits 16-18) INDIVIDUAL ADDRESS The least significant bit of the Individual Address must be zero for Ethernet (see the Command Structure) However no enforcement of 0 is provided by the 82596 Thus an Individual Address with 1 as its least significant bit is a valid Individual Address in all aspects The default address length is 6 bytes long as in 802 3 If a different length is used the IA Setup command should be executed after the Configure command Configure The Configure command loads the 82596 with its operating parameters It allows changing some of the parameters by specifying a byte count less than the maximum number of configuration bytes (11 in the 82586 mode 14 in the 32-Bit Segmented and Linear modes) The 82596 configuration depends on its mode of operation When configuring the 12th byte (Byte 11 undefined) in 82586 mode this byte should be all ones In the 82586 mode the maximum number of configuration bytes is 12 Any number larger than 12 will be reduced to 12 and any number less than 4 will be increased to 4 The additional features of the serial side are disabled in the 82586 mode In both the 32-Bit Segmented and Linear modes there are four additional configuration bytes which hold parameters for additional 82596 features If these parameters are not accessed the 82596 will follow their default values For more detailed information refer to the 32-Bit LAN Components User's Manual 34 82596CA The format of the Configure command is shown in Figure 23 24 and 25 31 EL S I X X X Byte 1 Byte 5 Byte 9 X X X X X X X X X X X ODD WORD X X X X X X X 0 1 Byte 0 Byte 4 Byte 8 X X X X X X X X 16 15 0 C B OK A A15 Byte 3 Byte 7 X X X X X 0 0 EVEN WORD 0 0 0 0 0 0 0 0 0 LINK OFFSET Byte 2 Byte 6 Byte 10 0 00 A0 4 8 12 16 Figure 23 CONFIGURE 31 EL S I 0 0 0 Byte 1 Byte 5 Byte 9 Byte 13 ODD WORD 0 0 0 0 0 0 0 0 1 Byte 0 Byte 4 Byte 8 Byte 12 16 15 0 82586 Mode EVEN WORD 0 0 0 0 0 0 0 0 0 0 0 LINK OFFSET Byte 3 Byte 7 Byte 11 Byte 2 Byte 6 Byte 10 0 00 A0 4 8 12 16 C B OK A A15 Figure 24 CONFIGURE 31 EL S A31 Byte 3 Byte 7 Byte 11 X X X X X X X X X X X Byte 2 Byte 6 Byte 10 X X X X X I 0 0 0 ODD WORD 0 0 0 0 0 0 0 0 1 32-Bit Segmented Mode EVEN WORD 0 0 0 0 0 0 0 0 0 0 0 0 00 A0 4 Byte 1 Byte 5 Byte 9 Byte 13 Byte 0 Byte 4 Byte 8 Byte 12 8 12 16 20 16 15 0 C B OK A LINK ADDRESS LINK ADDRESS EL B C I S A Figure 25 CONFIGURE Linear Mode As per standard Command Block (see the NOP command for details) Indicates that the command was abnormally terminated due to a CU Abort control command If 1 then the command was aborted and if necessary it should be repeated If this bit is 0 the command was not aborted Reserved (zero in the 32-Bit Segmented and Linear Modes) The CONFIGURE command Value 2h Bits 19-28 CMD (bits 16-18) The interpretation of the fields follows 7 P 6 X 5 X 4 X 3 2 1 0 BYTE COUNT BYTE 0 BYTE CNT (Bits 0-3) PREFETCHED (Bit 7) Byte Count Number of bytes including this one that hold parameters to be configured Enable the 82596 to write the prefetched bit in all prefetch RBDs 35 82596CA NOTE The P bit is valid only in the new memory structure modes In 82586 mode this bit is disabled (i e prefetched mark) 7 MONITOR X X FIFO LIMIT 0 no BYTE 1 FIFO Limit (Bits 0-3) MONITOR (Bits 6-7) DEFAULT C8h 7 SAV BF 1 0 0 0 0 RESUME RD 0 0 FIFO limit Receive monitor options If the Byte Count of the configure command is less than 12 bytes then these Monitor bits are ignored BYTE 2 SAV BF (Bit 7) DEFAULT 40h RESUME RD (Bit 1) 0 Received bad frames are not saved in the memory 1 Received bad frames are saved in the memory 0 1 The 82596 does not reread the next CB on the list when a CU Resume Control Command is issued The 82596 will reread the next CB on the list when a CU Resume Control Command is issued This is available only on the 82596B stepping 0 LOOP BACK MODE PREAMBLE LENGTH NO SRC ADD INS ADDRESS LENGTH 7 BYTE 3 ADR LEN (Bits 0-2) NO SCR ADD INS (Bit 3) PREAM LEN (Bits 4-5) LP BCK MODE (Bits 6-7) DEFAULT 26h 7 BOF METD Address length (any kind) No Source Address Insertion In the 82586 this bit is called AL LOC Preamble length Loopback mode 0 EXPONENTIAL PRIORITY 0 LINEAR PRIORITY BYTE 4 LIN PRIO (Bits 0-2) EXP PRIO (Bits 4-6) BOF METD (Bit 7) DEFAULT 00h 7 Linear Priority Exponential Priority Exponential Backoff method 0 INTER FRAME SPACING BYTE 5 INTERFRAME SPACING DEFAULT 60h Interframe spacing 36 82596CA 7 SLOT TIME - LOW 0 BYTE 6 SLOT TIME (L) DEFAULT 00h 7 MAXIMUM RETRY NUMBER 0 SLOT TIME - HIGH Slot time low byte 0 BYTE 7 SLOT TIME (H) (Bits 0-2) RETRY NUM (Bits 4-7) DEFAULT F2h 7 PAD BIT STUFF CRC16 CRC32 NO CRC INSER TONO CRS MAN NRZ BC DIS PRM MODE Slot time high part Number of transmission retries on collision 0 BYTE 8 PRM (Bit 0) BC DIS (Bit 1) MANCH NRZ (Bit 2) TONO CRS (Bit 3) NOCRC INS (Bit 4) CRC-16 CRC-32 (Bit 5) BIT STF (Bit 6) PAD (Bit 7) DEFAULT 00h 7 CDT SRC Promiscuous mode Broadcast disable Manchester or NRZ encoding See specific timing requirements for TXC in Manchester mode Transmit on no CRS No CRC insertion CRC type Bit stuffing Padding 0 COLLISION DETECT FILTER CRS SRC CARRIER SENSE FILTER BYTE 9 CRSF (Bits 0-2) CRS SRC (Bit 3) CDTF (Bits 4-6) CDT SRC (Bit 7) DEFAULT 00h Carrier Sense filter (length) Carrier Sense source Collision Detect filter (length) Collision Detect source 37 82596CA 7 MINIMUM FRAME LENGTH 0 BYTE 10 MIN FRAME LEN DEFAULT 40h 7 MONITOR MC ALL CDBSAC AUTOTX CRCINM LNGFLD PRECRS Minimum frame length 0 BYTE 11 PRECRS (Bit 0) LNGFLD (Bit 1) CRCINM (Bit 2) AUTOTX (Bit 3) CDBSAC (Bit 4) MC ALL (Bit 5) MONITOR (Bits 6-7) DEFAULT FFH 7 0 FDX 0 0 0 0 0 0 Preamble until Carrier Sense Length field Enables padding at the End-of-Carrier framing (802 3) Rx CRC appended to the frame in memory Auto retransmit when a collision occurs during the preamble Collision Detect by source address recognition Enable to receive all MC frames Receive monitor options 0 BYTE 12 FDX (Bit 6) DEFAULT 00h 7 DIS BOF MULT IA Enables Full Duplex operation 0 1 1 1 1 1 1 BYTE 13 MULT IA (Bit 6) DIS BOF (Bit 7) DEFAULT 3Fh Multiple individual address Disable the backoff algorithm 38 82596CA A reset (hardware or software) configures the 82596 according to the following defaults Table 4 Configuration Defaults Parameter ADDRESS LENGTH A L FIELD LOCATION AUTO RETRANSMIT BITSTUFFING EOC BROADCAST DISABLE CDBSAC CDT FILTER CDT SRC CRC IN MEMORY CRC-16 CRC-32 CRS FILTER CRS SRC DISBOF EXT LOOPBACK EXPONENTIAL PRIORITY EXPONENTIAL BACKOFF METHOD FULL DUPLEX (FDX) FIFO THRESHOLD INT LOOPBACK INTERFRAME SPACING LINEAR PRIORITY LENGTH FIELD MIN FRAME LENGTH MC ALL MONITOR MANCHESTER NRZ MULTI IA NUMBER OF RETRIES NO CRC INSERTION PREFETCH BIT IN RBD PREAMBLE LENGTH Preamble Until CRS PROMISCUOUS MODE PADDING SLOT TIME SAVE BAD FRAME TRANSMIT ON NO CRS Default Value 6 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 8 0 96 0 1 64 1 11 0 0 15 0 0 7 1 0 0 512 0 0 Units Meaning Bytes Located in FD Auto Retransmit Enable EOC Broadcast Reception Enabled Disabled Bit Times External Collision Detection CRC Not Transferred to Memory CRC-32 0 Bit Times External CRS Backoff Enabled Disabled 802 3 Algorithm 802 3 Algorithm CSMA CD Protocol (No FDX) TX 32 Bytes RX 64 Bytes Disabled Bit Times 802 3 Algorithm Padding Disabled Bytes Disabled Disabled NRZ Disabled Maximum Number of Retries CRC Appended to Frame Disabled (Valid Only in New Modes) Bytes Disabled Address Filter On No Padding Bit Times Discards Bad Frames Disabled NOTES 1 This configuration setup is compatible with the IEEE 802 3 specification 2 The Asterisk `` '' signifies a new configuration parameter not available in the 82586 3 The default value of the Auto retransmit configuration parameter is enabled(1) 4 Double Asterisk `` '' signifies IEEE 802 3 requirements 39 82596CA Multicast-Setup This command is used to load the 82596 with the Multicast-IDs that should be accepted As noted previously the filtering done on the Multicast-IDs is not perfect and some unwanted frames may be accepted This command resets the current filter and reloads it with the specified Multicast-IDs The format of the Multicastaddresses setup command is 31 EL S X X 4th byte MULTICAST ADDRESSES LIST Nth byte I X X X ODD WORD X X X X X X X 0 1 MC COUNT 16 15 1 C A15 B OK A 0 EVEN WORD 0 0 0 0 0 0 0 0 0 0 LINK OFFSET 0 0 A0 1st byte Figure 26 MC Setup 31 EL S A31 2nd byte Nth byte I 0 0 0 ODD WORD 0 0 0 0 0 0 0 0 82586 and 32-Bit Segmented Modes 16 15 1 1 C B OK A X 0 LINK ADDRESS 1st byte X MC COUNT EVEN WORD 0 0 0 0 0 0 0 0 0 0 0 0 A0 MULTICAST ADDRESSES LIST Figure 27 MC Setup where LINK ADDRESS EL B C I S A Linear Mode As per standard Command Block (see the NOP command for details) Indicates that the command was abnormally terminated due to a CU Abort control command If one then the command was aborted and if necessary it should be repeated If this bit is zero the command was not aborted Reserved (0 in both the 32-Bit Segmented and Linear Modes) The MC SETUP command value 3h This 14-bit field indicates the number of bytes in the MC LIST field The MC CNT must be a multiple of the ADDR LEN otherwise the 82596 reduces the MC CNT to the nearest ADDR LEN multiple MC CNT e 0 implies resetting the Hash table which is equivalent to disabling the Multicast filtering mechanism A list of Multicast Addresses to be accepted by the 82596 The least significant bit of each MC address must be 1 Bits 19-28 CMD (bits 16-18) MC-CNT MC LIST NOTE The list is sequential i e the most significant byte of an address is immediately followed by the least significant byte of the next address When the 82596 is configured to recognize multiple Individual Address (Multi-IA) the MC-Setup command is also used to set up the Hash table for the individual address The least significant bit in the first byte of each IA address must be 0 40 82596CA Transmit This command is used to transmit a frame of user data onto the serial link The format of a Transmit command is as follows 31 EL S A15 4th byte LENGTH FIELD I ODD WORD XXXXXXXX TBD OFFSET X X 1 0 16 15 0 C B A0 A15 6th byte EVEN WORD STATUS BITS LINK OFFSET MAXCOLL 0 0 A0 4 1st byte 8 12 DESTINATION ADDRESS Figure 28 TRANSMIT 31 EL S A15 0 0 0 0 0 0 4th byte LENGTH FIELD I 0 0 0 ODD WORD 0 0 0 0 0 0 0 0 0 NC SF 1 0 0 0 0 0 0 TBD OFFSET 16 15 0 C B A0 A15 0 EOF 0 82586 Mode EVEN WORD STATUS BITS LINK OFFSET TCB COUNT MAXCOLL 0 0 A0 4 8 1st byte 12 16 DESTINATION ADDRESS 6th byte OPTIONAL DATA Figure 29 TRANSMIT 31 EL S A31 A31 0 0 0 0 0 0 0 0 0 0 4th byte LENGTH FIELD 0 0 0 0 I 0 0 0 ODD WORD 0 0 0 0 0 NC SF 1 0 32-Bit Segmented Mode EVEN WORD B STATUS BITS MAXCOLL 0 0 A0 4 A0 8 TCB COUNT 12 1st byte 16 20 16 15 0 C LINK ADDRESS TRANSMIT BUFFER DESCRIPTOR ADDRESS 0 0 EOF 0 DESTINATION ADDRESS 6th byte OPTIONAL DATA Figure 30 TRANSMIT 31 EL S I 0 0 COMMAND WORD 0 0 0 0 0 0 NC SF 1 0 16 02 Linear Mode 0 No CRC Insertion disable when the 0 Simplified Mode all the Tx data is in configure command is configured to the Transmit Command Block The not insert the CRC during Transmit Buffer Descriptor Address transmission the NC bit has no field is all 1s effect 1 Flexible Mode Data is in the TCB and 1 No CRC Insertion enable when the in a linked list of TBDs configure command is configured to insert the CRC during transmission the CRC will not be inserted when NC e 1 uu 41 82596CA where EL B C I S OK (Bit 13) A (Bit 12) As per standard Command Block (see the NOP command for details) Error free completion Indicates that the command was abnormally terminated due to CU Abort control command If 1 then the command was aborted and if necessary it should be repeated If this bit is 0 the command was not aborted Reserved (0 in the 32-bit Segmented and Linear modes) The transmit command 4h Late collision A late collision (a collision after the slot time is elapsed) is detected No Carrier Sense signal during transmission Carrier Sense signal is monitored from the end of Preamble transmission until the end of the Frame Check Sequence for TONOCRS e 1 (Transmit On No Carrier Sense mode) it indicates that transmission has been executed despite a lack of CRS For TONOCRS e 0 (Ethernet mode) this bit also indicates unsuccessful transmission (transmission stopped when lack of Carrier Sense has been detected) Transmission unsuccessful (stopped) due to Loss of CTS Transmission unsuccessful (stopped) due to DMA Underrun i e the system did not supply data for transmission Transmission Deferred i e transmission was not immediate due to previous link activity Heartbeat Indicator Indicates that after a previously performed transmission and before the most recently performed transmission (Interframe Spacing) the CDT signal was monitored as active This indicates that the Ethernet Transceiver Collision Detect logic is performing properly The Heartbeat is monitored during the Interframe Spacing period Transmission attempt was stopped because the number of collisions exceeded the maximum allowable number of retries 0 (Reserved) The number of Collisions experienced during this frame Max Col e 0 plus S5 e 1 indicates 16 collisions As per standard Command Block (see the NOP Command for details) In the 82586 and 32-bit Segmented modes this is the offset of the first Tx Buffer Descriptor containing the data to be transmitted In the Linear mode this is the 32bit address of the first Tx Buffer Descriptor on the list If the TBD POINTER is all 1s it indicates that no TBD is used Contains the Destination Address of the frame The least significant bit (MC) indicates the address type MC e 0 Individual Address MC e 1 Multicast or Broadcast Address If the Destination Address bits are all 1s this is a Broadcast Address LENGTH FIELD The contents of this 2-byte field are user defined In 802 3 it contains the length of the data field It is placed in memory in the same order it is transmitted i e most significant byte first least significant byte second This 14-bit counter indicates the number of bytes that will be transmitted from the Transmit Command Block starting from the third byte after the TCB COUNT field (address n a 12 in the 32-bit Segmented mode N a 16 in the Linear mode) The TCB COUNT field can be any number of bytes (including an odd byte) this allows the user to transmit a frame with a header having an odd number of bytes The TCB COUNT field is not used in the 82586 mode Indicates that the whole frame is kept in the Transmit Command Block In the Simplified memory model it must be always asserted Bits 19-28 CMD (Bits 16-18) Status Bit 11 Status Bit 10 Status Bit 9 Status Bit 8 Status Bit 7 Status Bit 6 Status Bit 5 Status Bit 4 MAX-COL (Bits 3-0) LINK OFFSET TBD POINTER DEST ADDRESS TCB COUNT EOF Bit 42 82596CA The interpretation of what is transmitted depends on the No Source Address insertion configuration bit and the memory model being used NOTES 1 The Destination Address and the Length Field are sequential The Length Field immediately follows the most significant byte of the Destination Address 2 In case the 82596 is configured with No Source Address insertion bit equal to 0 the 82596 inserts its configured Source Address in the transmitted frame In the 82586 mode or when the Simplified memory model is used the Destination and Length fields of the transmitted frame are taken from the Transmit Command Block If the FLEXIBLE memory model is used the Destination and Length fields of the transmitted frame can be found either in the TCB or TBD depending on the TCB COUNT 3 If the 82596 is configured with the Address Length Field Location equal to 1 the 82596 does not insert its configured Source Address in the transmitted frame The first (2 c Address Length) a 2 bytes of the transmitted frame are interpreted as Destination Address Source Address and Length fields respectively The location of the first transmitted byte depends on the operational mode of the 82596 In the 82586 mode it is always the first byte of the first Tx Buffer In both the 32-bit Segmented and Linear modes it depends on the SF bit and TCB COUNT In the Simplified memory mode the first transmitted byte is always the third byte after the TCB COUNT field In the Flexible mode if the TCB COUNT is greater than 0 then it is the third byte after the TCB COUNT field If TCB COUNT equals 0 then it is first byte of the first Tx Buffer Transmit frames shorter than six bytes are invalid The transmission will be aborted (only in 82586 mode) because of a DMA Underrun 4 Frames which are aborted during transmission are jammed Such an interruption of transmission can be caused by any reason indicated by any of the status bits 8 9 10 and 12 Jamming Rules 1 Jamming will not start before completion of preamble transmission 2 Collisions detected during transmission of the last 11 bits will not result in jamming The format of a Transmit Buffer Descriptor is 82586 Mode 31 XX X X X X ODD WORD NEXT TBD OFFSET X X 16 15 EOF X 13 EVEN WORD SIZE (ACT COUNT) 0 0 4 TRANSMIT BUFFER ADDRESS 32-Bit Segmented Mode 31 ODD WORD NEXT TBD OFFSET 16 15 EOF 0 TRANSMIT BUFFER ADDRESS 13 EVEN WORD SIZE (ACT COUNT) 0 0 4 Linear Mode 31 0 0 0 0 0 0 ODD WORD 0 0 0 0 0 0 0 0 0 16 15 0 EOF 0 13 EVEN WORD SIZE (ACT COUNT) 0 0 4 8 NEXT TBD ADDRESS TRANSMIT BUFFER ADDRESS Figure 31 43 82596CA where EOF SIZE (ACT COUNT) NEXT TBD ADDRESS This bit indicates that this TBD is the last one associated with the frame being transmitted It is set by the CPU before transmit This 14-bit quantity specifies the number of bytes that hold information for the current buffer It is set by the CPU before transmission In the 82586 and 32-bit Segmented modes it is the offset of the next TBD on the list In the Linear mode this is the 32-bit address of the next TBD on the list It is meaningless if EOF e 1 The starting address of the memory area that contains the data to be sent In the 82586 mode this is a 24-bit address (A31 - A24 are considered to be zero) In the 32-bit Segmented and Linear modes this is a 32-bit address This buffer can be byte aligned for the 82596 B step BUFFER ADDRESS TDR This operation activates Time Domain Reflectomet which is a mechanism to detect open or short circuits on the link and their distance from the diagnosing station The TDR command has no parameters The TDR transmit sequence was changed compared to the 82586 to form a regular transmission The TDR command is designed to be used statically Make sure that both the CU and RU are idle before attempting a TDR command The TDR bit stream is as follows Preamble Source address Another Source address (the TDR frame is transmitted back to the sending station so DEST ADR e SRC ADR) Data field containing 7Eh patterns Jam Pattern which is the inverse CRC of the transmitted frame Maximum length of the TDR frame is 2048 bits If the 82596 senses collision while transmitting the TDR frame it transmits the jam pattern and stops the transmission The 82596 then triggers an internal timer (STC) the timer is reset at the beginning of transmission and reset if CRS is returned The timer measures the time elapsed from the start of transmission until an echo is returned The echo is indicated by Collision Detect going active or a drop in the Carrier Sense signal The following table lists the possible cases that the 82596 is able to analyze Conditions of TDR as Interpreted by the 82596 Transceiver Type Condition Carrier Sense was inactive for 2048-bit-time periods Carrier Sense signal dropped Collision Detect went active The Carrier Sense Signal did not drop or the Collision Detect did not go active within 2048-bit time period Ethernet Short or Open on the Transceiver Cable Short on the Ethernet cable Open on the Ethernet cable No Problem NA NA Open on the Serial Link No Problem Non Ethernet An Ethernet transceiver is defined as one that returns transmitted data on the receive pair and activates the Carrier Sense Signal while transmitting A Non-Ethernet Transceiver is defined as one that does not do so 44 82596CA The format of the Time Domain Reflectometer command is 82586 and 32-Bit Segmented Modes 31 EL S I X LNK XVR ET ET X OK PRB OPN SRT ODD WORD XXXXXXXXX1 TIME (11 bits) 0 16 15 1 C B OK 0 A15 0 EVEN WORD 0 0 0 0 0 0 0 0 0 0 LINK OFFSET 0 0 A0 Linear Mode 31 EL S A31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I 0 0 0 ODD WORD 0 0 0 0 0 0 0 1 0 0 16 15 1 0 C B OK 0 XVR PRB 0 LINK ADDRESS LNK OK ET OPN ET SRT X TIME (11 bits) EVEN WORD 0 0 0 0 0 0 0 0 0 0 0 0 A0 Figure 32 TDR where LINK ADDRESS EL B C I S A As per standard Command Block (see the NOP command for details) Indicates that the command was abnormally terminated due to CU Abort control command If one then the command was aborted and if necessary it should be repeated If this bit is zero the command was not aborted Reserved (0 in the 32-bit Segmented and Linear Modes) The TDR command Value 5h An 11-bit field that specifies the number of TxC cycles that elapsed before an echo was observed No echo is indicated by a reception consisting of ``1s'' only Because the network contains various elements such as transceiver links transceivers Ethernet repeaters etc the TIME is not exactly proportional to the problems distance No link problem identified TIME e 7FFh Indicates a Transceiver problem Carrier Sense was inactive for 2048-bit time period LNK OK e 0 TIME e 7FFh The transmission line is not properly terminated Collision Detect went active and LNK OK e 0 There is a short circuit on the transmission line Carrier Sense Signal dropped and LNK OK e 0 Bits 19-28 CMD (Bits 16-18) TIME LNK OK (Bit 15) XCVR PRB (Bit 14) ET OPN (Bit 13) ET SRT (Bit 12) 45 82596CA DUMP This command causes the contents of various 82596 registers to be placed in a memory area specified by the user It is supplied as a 82596 self-diagnostic tool and to provide registers of interest to the user The format of the DUMP command is 82586 and 32-Bit Segmented Modes 31 EL S A15 I X X X ODD WORD X X X X X X X 1 1 BUFFER OFFSET 16 15 0 C B OK 0 0 A0 A15 EVEN WORD 0 0 0 0 0 0 0 0 0 0 LINK OFFSET 0 0 A0 Linear Mode 31 EL S A31 A31 I X X X ODD WORD X X X X X X X 1 1 16 15 0 C B OK 0 0 LINK ADDRESS BUFFER ADDRESS EVEN WORD 0 0 0 0 0 0 0 0 0 0 0 0 A0 A0 Figure 33 Dump where LINK ADDRESS EL B C I S OK Bits 19-28 CMD (Bits 16-18) BUFFER POINTER As per standard Command Block (see the NOP command for details) Indicates error free completion Reserved (0 in the 32-bit Segmented and Linear Modes) The Dump command Value 6h In the 82586 and 32-bit Segmented modes this is the 16-bit-offset portion of the dump area address In the Linear mode this is the 32-bit linear address of the dump area Dump Area Information Format The 82596 is not Dump compatible with the 82586 because of the 32-bit internal architecture In 82586 mode the 82596 will dump the same number of bytes as the 82586 The compatible data will be marked with an asterisk In 82586 mode the dump area is 170 bytes The DUMP area format of the 32-bit Segmented and Linear modes is described in Figure 35 The size of the dump area of the 32-bit Segmented and Linear modes is 304 bytes When the Dump is executed by the Port command an extra word will be appended to the Dump Area The extra word is a copy of the Dump Area status word (containing the C B and OK Bits) The C and OK Bits are set when the 82596 has completed the Port Dump command 46 82596CA 15 14 13 12 11 10 9 8 7 6 5 4 DMA CONTROL REGISTER CONFIGURE BYTES 3 2 CONFIGURE BYTES 5 4 CONFIGURE BYTES 7 6 CONFIGURE BYTES 9 8 CONFIGURE BYTES 10 I A BYTES 1 0 I A BYTES 3 2 I A BYTES 5 4 LAST T X STATUS T X CRC BYTES 1 0 T X CRC BYTES 3 2 R X CRC BYTES 1 0 R X CRC BYTES 3 2 R X TEMP MEMORY 1 0 R X TEMP MEMORY 3 2 R X TEMP MEMORY 5 4 LAST RECEIVED STATUS HASH REGISTER BYTES 1 0 HASH REGISTER BYTES 3 2 HASH REGISTER BYTES 5 4 HASH REGISTER BYTES 7 6 SLOT TIME COUNTER WAIT TIME COUNTER MICRO MACHINE REGISTER FILE 60 BYTES MICRO MACHINE LFSR MICRO MACHINE FLAG ARRAY 14 BYTES QUEUE MEMORY CU PORT 8 BYTES MICRO MACHINE ALU RESERVED M M TEMP A ROTATE R 3 2 1 0 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 The 82596 is not Dump compatible with the 82586 because of the 32-bit internal architecture In 82586 mode the 82596 will dump the same number of bytes as the 82586 These bytes are not user defined results may vary from Dump command to Dump command 6A 6C 6E 7A 7C 82 84 86 88 8A 8C 8E 90 92 94 96 98 9A 9C 9E A0 A2 A4 A6 A8 M M TEMP A T X DMA BYTE COUNT M M INPUT PORT ADDRESS T X DMA ADDRESS M M OUTPUT PORT R X DMA BYTE COUNT M M OUTPUT PORT ADDRESS REGISTER R DMA ADDRESS RESERVED BUS THROTTLE TIMERS DIU CONTROL REGISTER RESERVED DMA CONTROL REGISTER BIU CONTROL REGISTER M M DISPATCHER REG M M STATUS REGISTER Figure 34 Dump Area Format 82586 Mode 47 82596CA 31 CONFIGURE BYTES 5 4 3 2 CONFIGURE BYTES 9 8 7 6 CONFIGURE BYTES 13 12 11 10 I A BYTES 1 0 X X X X X X X 0 00 04 08 X 0C 10 LAST T X STATUS TX CRC BYTES 3 2 RX CRC BYTES 3 2 14 18 1C 20 24 28 2C 30 34 The 82596 is not Dump compatible with the 82586 because of the 32-bit internal architecture In 82586 mode the 82596 will dump the same number of bytes as the 82586 These bytes are not user defined results may vary from Dump command to Dump command I A BYTES 5 2 TX CRC BYTES 0 1 RX CRC BYTES 0 1 RX TEMP MEMORY 1 0 R X TEMP MEMORY 5 2 HASH REGISTERS 1 0 LAST R X STATUS HASH REGISTER BYTES 5 2 SLOT TIME COUNTER RECEIVE FRAME LENGTH HASH REGISTERS 7 6 WAIT-TIME COUNTER MICRO MACHINE REGISTER FILE 128 BYTES MICRO MACHINE LFSR MICRO MACHINE FLAG ARRAY 28 BYTES M M INPUT PORT 16 BYTES MICRO MACHINE ALU RESERVED M M TEMP A ROTATE R M M TEMP A T X DMA BYTE COUNT M M INPUT PORT ADDRESS REGISTER T X DMA ADDRESS M M OUTPUT PORT REGISTER R X DMA BYTE COUNT M M OUTPUT PORT ADDRESS REGISTER R X DMA ADDRESS REGISTER RESERVED BUS THROTTLE TIMERS DIU CONTROL REGISTER RESERVED DMA CONTROL REGISTER BIU CONTROL REGISTER M M DISPATCHER REG M M STATUS REGISTER B0 B4 B8 D0 D4 E0 E4 E8 EC F0 F4 F8 FC 100 104 108 10C 110 114 118 11C 120 124 128 12C Figure 35 Dump Area Format Linear and 32-Bit Segmented Mode 48 82596CA Diagnose The Diagnose Command triggers an internal self-test procedure that checks internal 82596 hardware which includes Exponential Backoff Random Number Generator (Linear Feedback Shift Register) Exponential Backoff Timeout Counter Slot Time Period Counter Collision Number Counter Exponential Backoff Shift Register Exponential Backoff Mask Logic Timer Trigger Logic This procedure checks the operation of the Backoff block which resides in the serial side and is not easily controlled The Diagnose command is performed in two phases The format of the 82596 Diagnose command is 82586 and 32-Bit Segmented Modes 31 EL S X X I X X X X X X X ODD WORD X X X X X X X X X X X X X X 1 X 1 X 16 15 1 C B OK 0 F X A15 EVEN WORD 0 0 0 0 0 0 0 0 0 0 LINK OFFSET 0 0 A0 Linear Mode 31 EL S A31 I 0 0 0 ODD WORD 0 0 0 0 0 0 0 1 1 16 15 1 C B OK 0 F LINK ADDRESS EVEN WORD 0 0 0 0 0 0 0 0 0 0 0 0 A0 Figure 36 Diagnose where LINK ADDRESS EL B C I S Bits 19-28 CMD (bits 16-18) OK (bit 13) F (bit 11) As per standard Command Block (see the NOP command for details) Reserved (0 in the 32-bit Segmented and Linear Modes) The Diagnose command Value 7h Indicates error free completion Indicates that the self-test procedure has failed 49 82596CA RECEIVE FRAME DESCRIPTOR Each received frame is described by one Receive Frame Descriptor (see Figure 37) Two new memory structures are available for the received frames The structures are available only in the Linear and 32-bit Segmented modes Simplified Memory Structure The first is the Simplified memory structure the data section of the received frame is part of the RFD and is located immediately after the Length Field Receive Buffer Descriptors are not used with the Simplified structure it is primarily used to make programming easier If the length of the data area described in the Size Field is smaller than the incoming frame the following happens 1 The received frame is truncated 2 The No Resource error counter is updated 3 If the 82596 is configured to Save Bad Frames the RFD is not reused otherwise the same RFD is used to hold the next received frame and the only action taken regarding the truncated frame is to update the counter 4 The 82596 continues to receive the next frame in the next RFD 290218 - 15 Figure 37 The Receive Frame Area 50 82596CA Note that this sequence is very useful for monitoring If the 82596 is configured to Save Bad Frames to receive in Promiscuous mode and to use the Simplified memory structure any programmed length of received data can be saved in memory The Simplified memory structure is shown in Figure 38 290218 - 16 Figure 38 RFA Simplified Memory Structure Flexible Memory Structure The second structure is the Flexible memory structure the data structure of the received frame is stored in both the RFD and in a linked list of Receive Buffers Receive Buffer Descriptors The received frame is placed in the RFD as configured in the Size field Any remaining data is placed in a linked list of RBDs The Flexible memory structure is shown in Figure 39 51 82596CA 290218 - 17 Figure 39 RFA Flexible Memory Structure Buffers on the receive side can be different lengths The 82596 will not place more bytes into a buffer than indicated in the associated RBD The 82596 will fetch the next RBD before it is needed The 82596 will attempt to receive frames as long as the FBL is not exhausted If there are no more buffers the 82596 Receive Unit will enter the No Resources state Before starting the RU the CPU must place the FBL pointer in the RBD pointer field of the first RFD All remaining RBD pointer fields for subsequent RFDs should be ``1s '' If the Receive Frame Descriptor and the associated Receive Buffers are not reused (e g the frame is properly received or the 82596 is configured to Save Bad Frames) the 82596 writes the address of the next free RBD to the RBD pointer field of the next RFD Receive Buffer Descriptor (RBD) The RBDs are used to store received data in a flexible set of linked buffers The portion of the frame's data field that is outside the RFD is placed in a set of buffers chained by a sequence of RBDs The RFD points to the first RBD and the last RBD is flagged with an EOF bit set to 1 Each buffer in the linked list of buffers related to a particular frame can be any size up to 214 bytes but must be word aligned (begin on an even numbered byte) This ensures optimum use of the memory resources while maintaining low overhead All buffers in a frame are filled with the received data except for the last in which the actual count can be smaller than the allocated buffer space 52 82596CA 31 EL S X A15 4th byte SOURCE ADDRESS 6th byte X X X X X X X X X ODD WORD X X X X X X X X X RBD OFFSET 16 15 X C B OK 0 A0 A15 1st byte 6th byte 4th byte EVEN WORD STATUS BITS LINK OFFSET 0 0 0 0 0 0 00 A0 4 1st byte 8 12 16 DESTINATION ADDRESS X X X X X X X X X X LENGTH FIELD 20 Figure 40 Receive Frame Descriptor 31 EL S A15 0 0 4th byte SOURCE ADDRESS 6th byte 0 0 0 0 ODD WORD 0 0 0 0 0 0 SF 0 0 RBD OFFSET SIZE 16 15 0 C B OK A0 A15 EOF F 1st byte 6th byte 4th byte 82586 Mode EVEN WORD STATUS BITS LINK OFFSET ACTUAL COUNT 0 0 A0 4 8 1st byte 12 16 20 LENGTH FIELD 24 DESTINATION ADDRESS OPTIONAL DATA AREA Figure 41 Receive Frame Descriptor 31 EL S A31 A31 0 0 4th byte SOURCE ADDRESS 6th byte 1st byte SIZE 0 0 0 0 ODD WORD 0 0 0 0 0 0 SF 0 0 16 15 0 C 32-Bit Segmented Mode EVEN WORD 0 0 A0 4 A0 8 ACTUAL COUNT 12 1st byte 16 20 24 LENGTH FIELD 28 B OK STATUS BITS LINK ADDRESS RECEIVE BUFFER DESCRIPTOR ADDRESS EOF F 6th byte 4th byte OPTIONAL DATA AREA DESTINATION ADDRESS Figure 42 Receive Frame Descriptor Linear Mode 53 82596CA where EL S SF When set this bit indicates that this RFD is the last one on the RDL When set this bit suspends the RU after receiving the frame This bit selects between the Simplified or the Flexible mode 0 1 C B Simplified mode all the RX data is in the RFD RBD ADDRESS field is all ``1s '' Flexible mode Data is in the RFD and in a linked list of Receive Buffer Descriptors This bit indicates the completion of frame reception It is set by the 82596 This bit indicates that the 82596 is currently receiving this frame or that the 82596 is ready to receive the frame It is initially set to 0 by the CPU The 82596 sets it to 1 when reception set up begins and to 0 upon completion The C and B bits are set during the same operation Frame received successfully without errors RFDs with bit 13 equal to 0 are possible only if the save bad frames configuration option is selected Otherwise all frames with errors will be discarded although statistics will be collected on them The results of the Receive operation Defined bits are Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Length error if configured to check length CRC error in an aligned frame Alignment error (CRC error in misaligned frame) Ran out of buffer space no resources DMA Overrun failure to acquire the system bus Frame too short OK (bit 13) STATUS No EOP flag (for Bit stuffing only) When the SF bit equals zero and the 82596 is configured to save bad frames this bit signals that the receive frame was truncated Otherwise it is zero Bits 2-4 Zeros Bit 1 When it is zero the destination address of the received frame matches the IA address When it is a 1 the destination address of the received frame did not match the individual address For example a multicast address or broadcast address will set this bit to a 1 Receive collision A collision is detected during reception and the collision occurred after the destination address was received A 16-bit offset (32-bit address in the Linear mode) to the next Receive Frame Descriptor The Link Address of the last frame can be used to form a cyclical list The offset (address in the Linear mode) of the first RBD containing the received frame data An RBD pointer of all ones indicates no RBD These fields are for the Simplified and Flexible memory models They are exactly the same as the respective fields in the Receive Buffer Descriptor See the next section for detailed explanation of their functions Multicast bit The contents of the destination address of the receive frame The field is 0 to 6 bytes long The contents of the Source Address field of the received frame It is 0 to 6 bytes long The contents of this 2-byte field are user defined In 802 3 it contains the length of the data field It is placed in memory in the same order it is received i e most significant byte first least significant byte second Bit 0 LINK ADDRESS RBD POINTER EOF F SIZE ACT COUNT MC DESTINATION ADDRESS SOURCE ADDRESS LENGTH FIELD 54 82596CA NOTES 1 The Destination address Source address and Length fields are packed i e one field immediately follows the next 2 The affect of Address Length Location (No Source Address Insertion) configuration parameter while receiving is as follows 82586 Mode The Destination address Source address and Length field are not used they are placed in the RX data buffers 32-Bit Segmented and Linear Modes when the Simplified memory model is used the Destination address Source address and Length fields reside in their respective fields in the RFD When the Flexible memory strucrture is used the Destination address Source address and Length field locations depend on the SIZE field of the RFD They can be placed in the RFD in the RX data buffers or partially in the RFD and the rest in the RX data buffers depending on the SIZE field value 82586 Mode 31 A15 XX XX X X X X X X X X ODD WORD NEXT RBD OFFSET X X X A23 X X X X X X X X X 16 15 A0 EOF F EL X EVEN WORD ACTUAL COUNT SIZE 0 0 A0 4 8 RECEIVE BUFFER ADDRESS 32-Bit Segmented Mode 31 A15 A31 0 0 0 0 0 0 0 0 0 0 0 0 ODD WORD NEXT RBD OFFSET 0 0 0 16 15 A0 EOF F RECEIVE BUFFER ADDRESS 0 EL P SIZE EVEN WORD ACTUAL COUNT 0 0 A0 4 8 Linear Mode 31 0 A31 A31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODD WORD 0 0 0 0 0 0 0 0 0 16 15 0 EOF F NEXT RBD ADDRESS RECEIVE BUFFER ADDRESS 0 0 0 EL P SIZE EVEN WORD ACTUAL COUNT 0 0 A0 4 A0 8 Figure 43 Receive Buffer Descriptor 55 82596CA where EOF Indicates that this is the last buffer related to the frame It is cleared by the CPU before starting the RU and is written by the 82596 at the end of reception of the frame Indicates that this buffer has already been used The Actual Count has no meaning unless the F bit equals one This bit is cleared by the CPU before starting the RU and is set by the 82596 after the associated buffer has been This bit has the same meaning as the Complete bit in the RFD and CB This 14-bit quantity indicates the number of meaningful bytes in the buffer It is cleared by the CPU before starting the RU and is written by the 82596 after the associated buffer has already been used In general after the buffer is full the Actual Count value equals the size field of the same buffer For the last buffer of the frame Actual Count can be less than the buffer size The offset (absolute address in the Linear mode) of the next RBD on the list It is meaningless if EL e 1 The starting address of the memory area that contains the received data In the 82586 mode this is a 24-bit address (with pins A24 - A31 e 0) In the 32-bit Segmented and Linear modes this is a 32-bit address Indicates that the buffer associated with this RBD is last in the FBL This bit indicates that the 82596 has already prefetched the RBDs and any change in the RBD data will be ignored This bit is valid only in the new 82596 memory modes and if this feature has been enabled during configure command The 82596 Prefetches the RBDs in locked cycles after prefetching the RBD the 82596 performs a write cycle where the P bit is set to one and the rest of the data remains unchanged The CPU is responsible for resetting it in all RBDs The 82596 will not check this bit before setting it This 14-bit quantity indicates the size in bytes of the associated buffer This quantity must be an even number F ACT COUNT NEXT BD ADDRESS BUFFER ADDRESS EL P SIZE 56 82596CA PGA PACKAGE THERMAL SPECIFICATION Parameter iJC iJA Thermal Resistance 3C W 24 C W NOTICE This is a production data sheet The specifications are subject to change without notice WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability ELECTRICAL AND TIMING CHARACTERISTICS Absolute Maximum Ratings b 65 C to a 150 C Storage Temperature Case Temperature under Bias b 65 C to a 110 C Supply Voltage with Respect to VSS b 0 5V to a 6 5V b 0 5V to VCC a 0 5V Voltage on Other Pins DC Characteristics TC e 0 C-85 C VCC e 5V g10% LE BE have MOS levels (see VMIL VMIH) All other signals have TTL levels (see VIL VIH VOL VOH) Symbol VIL VIH VMIL VMIH VOL VCIL VCIH VOH ILI ILO CIN COUT CCLK ICC ICC Parameter Input Low Voltage (TTL) Input High Voltage (TTL) Input Low Voltage (MOS) Input High Voltage (MOS) Output Low Voltage (TTL) RXC TXC Input Low Voltage RXC TXC Input High Voltage Output High Voltage (TTL) Input Leakage Current Output Leakage Current Capacitance of Input Buffer Capacitance of Input Output Buffer CLK Capacitance Power Supply Power Supply b0 5 Min b0 3 Max a0 8 Units V V V V V V V V Notes 20 b0 3 VCC a 0 3 a0 8 37 VCC a 0 3 0 45 06 VCC a 0 5 IOL e 4 0 mA 33 24 IOH e 0 9 mA - 1 mA 0 s VIN s VCC 0 45 k VOUT k VCC FC e 1 MHz FC e 1 MHz FC e 1 MHz At 25 MHz ICC Typical e 100 mA At 33 MHz ICC Typical e 150 mA g15 g15 mA mA pF pF pF mA mA 10 12 20 200 300 57 82596CA AC Characteristics 82596CA C-STEP INPUT OUTPUT SYSTEM TIMINGS TC e 0 C- a 85 C VCC e 5V g10% These timing assume the CL on all outputs is 50 pF unless otherwise specified CL can be 20 pF to 120 pF however timings must be derated All timing requirements are given in nanoseconds Symbol Parameter Operating Frequency T1 T1a T2 T3 T4 T5 T6 T6a T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T22a T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 CLK Period CLK Period Stability CLK High CLK Low CLK Rise Time CLK Fall Time BEn LOCK and A2-A31 Valid Delay BLAST PCHK Valid Delay BEn LOCK BLAST A2-A31 Float Delay W R and ADS Valid Delay W R and ADS Float Delay D0-D31 DPn Write Data Valid Delay D0-D31 DPn Write Data Float Delay HOLD Valid Delay CA and BREQ Setup Time CA and BREQ Hold Time BS16 Setup Time BS16 Hold Time BRDY RDY Setup Time BRDY RDY Hold Time D0-D31 DPn READ Setup Time D0-D31 DPn READ Hold Time AHOLD and HLDA Setup Time AHOLD Hold Time HLDA Hold Time RESET Setup Time RESET Hold Time INT INT Valid Delay CA and BREQ PORT Pulse Width D0-D31 CPU PORT Access Setup Time D0-D31 CPU PORT Access Hold Time PORT Setup Time PORT Hold Time BOFF Setup Time BOFF Hold Time 3 3 3 3 3 3 3 2 11 6 12 5 12 5 10 6 15 5 5 14 5 1 2 T1 10 6 11 5 12 5 23 123 2 2 2 2 2 2 20 20 8 8 23 32 39 23 39 27 39 30 12 12 2 2 2 2 2 2 12 12 12 12 12 16 MHz Min 12 5 MHz 62 5 Max 16 MHz 80 0 1% Adjacent CLK D 2 0V 0 8V 0 8V to 2 0V 2 0V to 0 8V Notes 1X CLK Input Timings shown are for the 82596CA C-Stepping For information regarding timings for the 82596CA A1 or B-Step contact your local Intel representative 58 82596CA AC Characteristics (Continued) 82596CA C-STEP INPUT OUTPUT SYSTEM TIMINGS TC e 0 C- a 85 C VCC e 5V g10% These timing assume the CL on all outputs is 50 pF unless otherwise specified CL can be 20 pF to 120 pF however timings must be derated All timing requirements are given in nanoseconds Symbol Parameter Operating Frequency T1 T1a T2 T3 T4 T5 T6 T6a T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T22a T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 CLK Period CLK Period Stability CLK High CLK Low CLK Rise Time CLK Fall Time BEn LOCK and A2-A31 Valid Delay BLAST PCHK Valid Delay BEn LOCK BLAST A2-A31 Float Delay W R and ADS Valid Delay W R and ADS Float Delay D0-D31 DPn Write Data Valid Delay D0-D31 DPn Write Data Float Delay HOLD Valid Delay CA and BREQ Setup Time CA and BREQ Hold Time BS16 Setup Time BS16 Hold Time BRDY RDY Setup Time BRDY RDY Hold Time D0-D31 DPn READ Setup Time D0-D31 DPn READ Hold Time AHOLD and HLDA Setup Time AHOLD Hold Time HLDA Hold Time RESET Setup Time RESET Hold Time INT INT Valid Delay CA and BREQ PORT Pulse Width D0-D31 CPU PORT Access Setup Time D0-D31 CPU PORT Access Hold Time PORT Setup Time PORT Hold Time BOFF Setup Time BOFF Hold Time 3 3 3 3 3 3 3 2 10 6 12 4 12 4 6 5 15 4 5 12 4 1 2 T1 6 5 10 5 12 4 23 123 2 2 2 2 2 2 16 16 6 6 20 25 34 20 34 23 34 25 12 12 2 2 2 2 2 2 12 12 12 12 12 20 MHz Min 12 5 MHz 50 Max 20 MHz 80 0 1% Adjacent CLK D 2 0V 0 8V 0 8V to 2 0V 2 0V to 0 8V Notes 1X CLK Input Timings shown are for the 82596CA C-Stepping For information regarding timings for the 82596CA A1 or B-Step contact your local Intel representative 59 82596CA AC Characteristics (Continued) 82596CA C-STEP INPUT OUTPUT SYSTEM TIMINGS TC e 0 C- a 85 C VCC e 5V g10% These timing assume the CL on all outputs is 50 pF unless otherwise specified CL can be 20 pF to 120 pF however timings must be derated All timing requirements are given in nanoseconds Symbol Parameter Operating Frequency T1 T1a T2 T3 T4 T5 T6 T6a T6b T6c T6d T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T17a T18 T19 T20 T21 T22 T22a T23 T24 T25 CLK Period CLK Period Stability CLK High CLK Low CLK Rise Time CLK Fall Time BEn Valid Delay BLAST Valid Delay LOCK Valid Delay A2-A31 Valid Delay PCHK Valid Delay BEn LOCK BLAST A2-A31 Float Delay W R and ADS Valid Delay W R and ADS Float Delay D0-D31 DPn Write Data Valid Delay D0-D31 DPn Write Data Float Delay HOLD Valid Delay CA and BREQ Setup Time CA and BREQ Hold Time BS16 Setup Time BS16 Hold Time BRDY Setup Time RDY Setup Time BRDY RDY Hold Time D0-D31 DPn READ Setup Time D0-D31 DPn READ Hold Time AHOLD and HLDA Setup Time AHOLD Hold Time HLDA Hold Time RESET Setup Time RESET Hold Time INT INT Valid Delay 3 3 3 3 3 3 3 3 3 3 3 7 3 8 3 9 8 3 6 45 10 3 3 10 3 1 20 14 14 4 4 17 20 18 18 24 30 19 30 20 30 19 12 12 2 2 2 2 2 2 2 12 12 12 12 12 25 MHz Min 12 5 MHz 40 Max 25 MHz 80 0 1% Adjacent CLK D 2 0V 0 8V 0 8V to 2 0V 2 0V to 0 8V Notes 1X CLK Input Timings shown are for the 82596CA C-Stepping For information regarding timings for the 82596CA A1 or B-Step contact your local Intel representative 60 82596CA AC Characteristics (Continued) 82596CA C-STEP INPUT OUTPUT SYSTEM TIMINGS TC e 0 C- a 85 C VCC e 5V g10% These timing assume the CL on all outputs is 50 pF unless otherwise specified CL can be 20 pF to 120 pF however timings must be derated All timing requirements are given in nanoseconds Symbol T26 T27 T28 T29 T30 T31 T32 Parameter CA and BREQ PORT Pulse Width D0-D31 CPU PORT Access Setup Time D0-D31 CPU PORT Access Hold Time PORT Setup Time PORT Hold Time BOFF Setup Time BOFF Hold Time 25 MHz Min 2 T1 6 45 7 3 10 3 Max Notes 123 2 2 2 2 2 2 Timings shown are for the 82596CA C-Stepping For information regarding timings for the 82596CA A1 or B-Step contact your local Intel representative 61 82596CA AC Characteristics (Continued) 82596CA C-STEP INPUT OUTPUT SYSTEM TIMINGS TC e 0 C to a 85 C VCC e 5V g5% These timing assume the CL on all outputs is 50 pF unless otherwise specified CL can be 20 pF to 120 pF however timings must be derated All timing requirements are given in nanoseconds Symbol Parameter Operating Frequency T1 T1a T2 T3 T4 T5 T6 T6a T6b T6c T6d T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T17a T18 T19 T20 T21 T21a T22 CLK Period CLK Period Stability CLK High CLK Low CLK Rise Time CLK Fall Time BEn Valid Delay BLAST Valid Delay LOCK Valid Delay A2-A31 Valid Delay PCHK Valid Delay BEn LOCK BLAST A2-A31 Float Delay W R and ADS Valid Delay W R and ADS Float Delay D0-D31 DPn Write Data Valid Delay D0-D31 DPn Write Data Float Delay HOLD Valid Delay CA and BREQ Setup Time CA and BREQ Hold Time BS16 Setup Time BS16 Hold Time BRDY Setup Time RDY Setup Time BRDY RDY Hold Time D0-D31 DPn READ Setup Time D0-D31 DPn READ Hold Time AHOLD Setup Time HLDA Setup Time AHOLD Hold Time 3 3 3 3 3 3 3 3 3 3 3 7 3 7 3 9 8 3 6 45 10 8 3 11 11 3 3 17 20 16 18 23 20 16 20 19 20 19 12 12 2 2 2 2 2 2 2 12 12 12 33 MHz Min 12 5 MHz 30 Max 33 MHz 80 0 1% Adjacent CLK D 2 0V 0 8V 0 8V to 2 0V 2 0V to 0 8V Notes 1X CLK Input Timings shown are for the 82596CA C-Stepping For information regarding timings for the 82596CA A1 or B-Step contact your local Intel representative 62 82596CA AC Characteristics (Continued) 82596CA C-STEP INPUT OUTPUT SYSTEM TIMINGS CL on all outputs is 50 pF unless otherwise specified All timing requirements are given in nanoseconds Symbol T22a T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 Parameter HLDA Hold Time RESET Setup Time RESET Hold Time INT INT Valid Delay CA and BREQ PORT Pulse Width D0-D31 CPU PORT Access Setup Time D0-D31 CPU PORT Access Hold Time PORT Setup Time PORT Hold Time BOFF Setup Time BOFF Hold Time 33 MHz Min 3 9 3 1 2T1 6 45 7 3 10 3 20 123 2 2 2 2 2 2 Max Notes 12 12 12 NOTES Timings shown are for the 82596CA C-stepping For information regarding timings for the 82596CA A1 or B-step contact your local Intel representative 1 RESET HLDA and CA are internally synchronized This timing is to guarantee recognition at next clock for RESET HLDA and CA 2 All set-up hold and delay timings are at maximum frequency specification Fmax and must be derated according to the following equation for operation at lower frequencies Tderated e (Fmax Fopr) c T where Tderate e Specifies the value to derate the specification Fmax e Maximum operating frequency Fopr e Actual operating frequency T e Specification at maximum frequency This calculation only provides a rough estimate for derating the frequency For more detailed information contact your Intel Sales Office for the data sheet supplement 3 CA pulse width need only be 1 T1 wide if the set up and hold times are met BREQ must meet setup and hold times and need only be 1 T1 wide TRANSMIT RECEIVE CLOCK PARAMETERS Symbol T36 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 T48 TxC Cycle TxC Rise Time TxC Fall Time TxC High Time TxC Low Time TxD Rise Time TxD Fall Time TxD Transition TxC Low to TxD Valid TxC Low to TxD Transition TxC High to TxD Transition TxC Low to TxD High (At End of Transition) 20 25 25 25 25 19 18 10 10 Parameter Min 50 5 5 20 MHz Max 13 1 1 13 13 4 4 24 46 24 24 4 63 Notes 82596CA TRANSMIT RECEIVE CLOCK PARAMETERS (Continued) Symbol RTS AND CTS PARAMETERS T49 T50 T51 T52 TxC Low to RTS Low Time to Activate RTS CTS Low to TxC Low CTS Setup Time TxC Low to CTS Invalid CTS Hold Time TxC Low to RTS High 10 25 25 20 7 5 5 Parameter Min 20 MHz Max Notes RECEIVE CLOCK PARAMETERS T53 T54 T55 T56 T57 RXC Cycle RXC Rise Time RXC Fall Time RXC High Time RXC Low Time 19 18 50 5 5 13 1 1 1 1 RECEIVED DATA PARAMETERS T58 T59 T60 T61 RXD Setup Time RXD Hold Time RXD Rise Time RXD Fall Time 20 10 10 10 6 6 CRS AND CDT PARAMETERS T62 T63 T64 T65 T66 T67 T68 T69 T70 CDT Low to TXC HIGH External Collision Detect Setup Time TXC High to CDT Inactive CDT Hold Time CDT Low to Jam Start CRS Low to TXC High Carrier Sense Setup Time TXC High to CRS Inactive CRS Hold Time (Internal Collision Detect) CRS High to Jamming Start Jamming Period CRS High to RXC High CRS Inactive Setup Time RXC High to CRS High CRS Inactive Hold Time 30 10 20 10 12 11 20 10 10 64 82596CA TRANSMIT RECEIVE CLOCK PARAMETERS (Continued) Symbol Parameter Min INTERFRAME SPACING PARAMETERS T71 Interframe Delay 9 20 MHz Max Notes EXTERNAL LOOPBACK-PIN PARAMETERS T72 T73 TXC Low to LPBK Low TXC Low to LPBK High T36 T36 4 4 NOTES 1 Special MOS levels VCIL e 0 9V and VCIH e 3 0V 2 Manchester only 3 Manchester Needs 50% duty cycle 4 1 TTL load a 50 pF 5 1 TTL load a 100 pF 6 NRZ only 7 Abnormal end of transmission CTS expires before RTS 8 Normal end to transmission 9 Programmable value T71 e NIFS T36 where NIFS e the IFS configuration value (if NIFS is less than 12 then NIFS is forced to 12) 10 Programmable value T64 e (NCDF T36) a x T36 (If the collision occurs after the preamble) where NCDF e the collision detect filter configuration value and x e 12 13 14 or 15 11 T68 e 32 T36 12 Programmable value T67 e (NCSF T36) a x T36 where NCSF e the Carrier Sense Filter configuration value and x e 12 13 14 or 15 13 To guarantee recognition on the next clock 65 82596CA 82596CA BUS OPERATION The following figures show the 82596CA basic bus cycle and basic burst cycle Please refer to the 32-Bit LAN Component User's Manual 290218 - 40 Figure 44 Basic 82596CA Bus Cycle 290218 - 41 Figure 45 Basic 82596CA Burst Cycle 66 82596CA SYSTEM INTERFACE A C TIMING CHARACTERISTICS The measurements should be done at TC e 0 C to a 85 C VCC e 5V g10% C e 50 pF unless otherwise specified A C testing inputs are driven at 2 4V for a logic ``1'' and 0 45V for a logic ``0'' Timing measurements are made at 1 5V for both logic ``1'' and ``0'' Rise and Fall time of inputs and outputs signals are measured between 0 8V and 2 0V respectively unless otherwise specified All timings are relative to CLK crossing the 1 5V level All A C parameters are valid only after 100 ms from power up 290218 - 18 290218 - 19 Figure 46 CLK Timings Two types of timing specifications are presented below 1 Input Timing minimum setup and hold times 2 Output Timings output delays and float times from CLK rising edge Figure 47 defines how the measurements should be done LEGEND Ts e Input Setup Time Th e Input Hold Time Tn e Minimum output delay or Mininum float delay Tx e Maximum output delay or Maximum float delay 290218 - 20 Figure 47 Drive Levels and Measurements Points for A C Specifications Ts Th Tn Tx e e e e T13 T15 T17 T19 T14 T16 T18 T20 T6 T6a T7 T8 T9 T6 T6a T7 T8 T9 T21 T22 T10 T10 T23 T27 T29 T31 T22a T24 T28 T30 T32 T11 T12 T25 T11 T12 T25 67 82596CA INPUT WAVEFORMS 290218 - 21 Figure 48 CA and BREQ Input Timing 290218 - 22 Figure 49 INT INT Output Timing 290218 - 23 Figure 50 HOLD HLDA Timings 290218 - 24 Figure 51 Input Setup and Hold Time 68 82596CA 290218 - 25 Figure 52 Output Valid Delay Timing 290218 - 26 Figure 53 Output Float Delay Timing 290218 - 27 Figure 54 PORT Setup and Hold Time 69 82596CA 290218 - 28 Figure 55 RESET Input Timing SERIAL AC TIMING CHARACTERISTICS 290218 - 29 Figure 56 Serial Input Clock Timing 290218 - 30 Figure 57 Transmit Data Waveforms 70 82596CA 290218 - 31 Figure 58 Transmit Data Waveforms 290218 - 32 Figure 59 Receive Data Waveforms (NRZ) 290218 - 33 Figure 60 Receive Data Waveforms (CRS) 71 82596CA OUTLINE DIAGRAMS 132 LEAD CERAMIC PIN GRID ARRAY PACKAGE INTEL TYPE A mm (inch) 290218 - 34 Family Ceramic Pin Grid Array Package Symbol Min A A1 A2 A3 B D D1 e1 L N S1 ISSUE 1 27 IWS 3 56 0 76 2 67 1 14 0 43 36 45 32 89 2 29 2 54 Millimeters Max 4 57 1 27 3 43 1 40 0 51 37 21 33 15 2 79 3 30 132 2 54 10 12 88 0 050 Solid Lid Solid Lid Notes Min 0 140 0 030 0 105 0 045 0 017 1 435 1 295 0 090 0 100 Inches Max 0 180 0 050 0 135 0 055 0 020 1 465 1 305 0 110 0 130 132 0 100 Solid Lid Solid Lid Notes 72 82596CA Intel Case Outline Drawings Plastic Quad Flat Pack (PQFP) 0 025 Inch (0 635mm) Pitch Symbol N A A1 DE D1 E1 D2 E2 D3 E3 D4 E4 L1 Issue Symbol N A A1 DE D1 E1 D2 E2 D3 E3 D4 E4 L1 Issue Description Leadcount Package Height Standoff Terminal Dimension Package Body Bumper Distance Lead Dimension Min Max 68 Min Max 84 Min Max Min Max Min Max Min Max 100 132 164 196 0 160 0 170 0 160 0 170 0 160 0 170 0 160 0 170 0 160 0 170 0 160 0 170 0 020 0 030 0 020 0 030 0 020 0 030 0 020 0 030 0 020 0 030 0 020 0 030 0 675 0 685 0 775 0 785 0 875 0 885 1 075 1 085 1 275 1 285 1 475 1 485 0 547 0 553 0 647 0 653 0 747 0 753 0 947 0 953 1 147 1 153 1 347 1 353 0 697 0 703 0 797 0 803 0 897 0 903 1 097 1 103 1 297 1 303 1 497 1 503 0 400 REF 0 500 REF 0 600 REF 0 800 REF 1 000 REF 1 200 REF Foot Radius Location 0 623 0 637 0 723 0 737 0 823 0 837 1 023 1 037 1 223 1 237 1 423 1 437 Foot Length 0 020 0 030 0 020 0 030 0 020 0 030 0 020 0 030 0 020 0 030 0 020 0 030 INCH Max 68 Min Max 84 Min Max Min Max Min Max Min Max IWS Preliminary 12 12 88 Description Leadcount Package Height Standoff Terminal Dimension Package Body Bumper Distance Lead Dimension Min 100 132 164 196 4 06 4 32 4 06 4 32 4 06 4 32 4 06 4 32 4 06 4 32 4 06 4 32 0 51 0 76 0 51 0 76 0 51 0 76 0 51 0 76 0 51 0 76 0 51 0 76 17 15 17 40 19 69 19 94 22 23 22 48 27 31 27 56 32 39 32 64 37 47 37 72 13 89 14 05 16 43 16 59 18 97 19 13 24 05 24 21 29 13 29 29 34 21 34 37 17 70 17 85 20 24 20 39 22 78 22 93 27 86 28 01 32 94 33 09 38 02 38 18 10 16 REF 12 70 REF 15 24 REF 20 32 REF 25 40 REF 30 48 REF Foot Radius Location 15 82 16 17 18 36 18 71 21 25 21 25 25 89 26 33 31 06 31 41 36 14 36 49 Foot Length 0 51 0 76 0 51 0 76 0 51 0 76 0 51 0 76 0 51 0 76 0 51 0 76 mm IWS Preliminary 12 12 88 73 82596CA mm (inch) Figure 61 Principal Dimensions and Datums 290218 - 35 mm (inch) Figure 62 Molded Details 290218 - 36 74 82596CA mm (inch) Figure 63 Terminal Details 290218 - 37 mm (inch) Detail J Figure 64 Typical Lead Detail L 290218 - 38 75 82596CA 290218 - 39 mm (inch) Figure 65 Detail M REVISION SUMMARY The following represents the key differences between version 004 and version 005 of the 82596CA Data Sheet 1 Timings added for -16 MHz and -20 MHz specfications The following represents the key differences between version 005 and version 006 of the 82596CA Data Sheet 1 A description of the 82596CA C-stepping enhancements was added and the 82596CA B-step information was removed 2 Description of BOFF pin changed BOFF may be asserted in T1 in the 82596 C-step 3 Recommendation to use only one type of buffer (either Simplified or Flexible) in any given linked list 4 Added detailed description regarding operation or RCVCDT counter 5 Added New Enhanced Big Endian Mode section The New Enhanced Big Endian Mode applies only to the 82596 C-stepping 6 Added programming recommendations regarding RU and CU Start commands These warn against Starting the CU while it is Active and Starting the RU while it is Ready 7 Emphasized that the TDR command is a static command and should not be used in an active network 8 Improved 82596CA C-step timings were added for all speeds 76 |
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